XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 44

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

Interrupts
4.4.3.3 Output Compare Interrupt
4.4.3.4 Timer Overflow Interrupt
Technical Data
44
the timer status register (TSR) and its corresponding enable bit can be
found in the timer control register (TCR).
The I bit in the CCR must be clear in order for the input capture interrupt
to be enabled. The interrupt service routine address is specified by the
contents of memory locations $3FF8 and $3FF9.
The output compare interrupt is generated by the 16-bit timer as
described in
is located in register TSR and its corresponding enable bit can be found
in register TCR.
The I bit in the CCR must be clear in order for the output compare
interrupt to be enabled. The interrupt service routine address is specified
by the contents of memory locations $3FF8 and $3FF9.
The timer overflow interrupt is generated by the 16-bit timer as described
in
register TSR and its corresponding enable bit can be found in register
TCR.
The I bit in the CCR must be clear in order for the timer overflow interrupt
to be enabled. This internal interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $3FF8 and $3FF9.
Section 8. 16-Bit
Section 8. 16-Bit
Interrupts
Timer. The timer overflow interrupt flag is located in
Timer. The output compare interrupt flag
MC68HC05P18A
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