XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 67

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XC68HC05P18A

Manufacturer Part Number
XC68HC05P18A
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet
MC68HC05P18A
MOTOROLA
Note: The counter and control registers are the only 16-bit timer registers affected by reset.
(EXTERNAL OR OTHER)
16-BIT FREE-RUNNING
16-BIT FREE-RUNNING
Note: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer
TIMER OVERFLOW
INTERNAL RESET
status register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register
pair (TCRL).
PH2 CLOCK
FLAG (TOF)
PH2 CLOCK
COUNTER
COUNTER
RESET
$FFFE
Figure 8-4. State Timing Diagram for Timer Overflow
Figure 8-5. State Timing Diagram for Timer Reset
of missing timer overflow interrupts due to clearing of the TOF. See
Figure
The free-running counter is initialized to $FFFC during reset and is a
read-only register. During power-on reset (POR), the counter is
initialized to $FFFC and begins counting after the oscillator startup
delay. Since the counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the counter repeats every 262,144 PH2 clock
cycles (524,288 oscillator cycles). When the free-running counter rolls
over from $FFFF to $0000, the timer overflow flag bit (TOF) in the timer
status register (TSR) is set. An interrupt can also be enabled when
counter rollover occurs by setting the timer overflow interrupt enable bit
(TOIE) in the timer control register (TCR). See
$FFFC
8-4.
$FFFF
16-Bit Timer
$FFFD
$0000
Figure
$FFFE
$0001
8-5.
Technical Data
16-Bit Timer
$0002
$FFFF
Timer
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