XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 80
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XC68HC05P18A
Manufacturer Part Number
XC68HC05P18A
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet
1.XC68HC05P18A.pdf
(130 pages)
- Current page: 80 of 130
- Download datasheet (2Mb)
Serial Input/Output Ports (SIOP)
9.4 SIOP Registers
9.4.1 SIOP Control Register
Technical Data
80
Address:
be transmitted in either most-significant bit (MSB) first format or the
least-significant bit (LSB) format.
On the first falling edge of SCK, the first data bit will be shifted out to the
SDO pin. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 ns before the rising edge of the SCK and remain valid for
100 ns after the rising edge of SCK. See
The SIOP is programmed and controlled by these registers:
This register is located at address $000A and contains two bits.
Figure 9-3
the value of each bit after reset.
Reset:
Read:
Write:
•
•
•
SIOP control register (SCR) located at address $000A
SIOP status register (SSR) located at address $000B
SIOP data register (SDR) located at address $000C
$000A
Bit 7
0
0
Serial Input/Output Ports (SIOP)
shows the position of each bit in the register and indicates
Figure 9-3. SIOP Control Register (SCR)
= Unimplemented
SPE
6
0
5
0
0
MSTR
4
0
Figure
3
0
0
9-2.
2
0
0
MC68HC05P18A
1
0
0
MOTOROLA
Bit 0
0
0
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