XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 42
XC68HC05P18A
Manufacturer Part Number
XC68HC05P18A
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet
1.XC68HC05P18A.pdf
(130 pages)
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Interrupts
4.4 Interrupt Types
4.4.1 Reset Interrupt Sequence
4.4.2 Software Interrupt (SWI)
Technical Data
42
The interrupts fall into these three categories which are discussed here:
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in
on the RESET pin or internally generated RST signal causes:
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction are
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $3FFC and $3FFD.
•
•
•
•
•
•
Reset interrupt sequence
Software interrupt (SWI)
Hardware interrupts
The program to vector to its starting address, which is specified by
the contents of memory locations $3FFE and $3FFF
The I bit in the condition code register (CCR) to be set
The MCU to be configured to a known state as described in
Section 5.
Resets.
Interrupts
Figure
4-1. A low-level input
MC68HC05P18A
MOTOROLA
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