MC9S12A256B ETC, MC9S12A256B Datasheet - Page 116

• Manufacturer Part Number: MC9S12A256B
• Description: device made up of standard HCS12 blocks and the HCS12 processor core
• Manufacturer: ETC

MC9S12DP256B Device User Guide — V02.14
Conditions are shown in Table A-4 unless otherwise noted, C
Num C
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
10
11
12
116
1
1
2
3
4
5
6
9
(CPOL 0)
(CPOL 1)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
Master and the Slave timing shown in Table A-19.
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
(INPUT)
P Operating Frequency
P SCK Period t
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid (after Enable Edge)
D Data Hold Time (Outputs)
D Rise Time Inputs and Outputs
D Fall Time Inputs and Outputs
MISO
MOSI
SCK
SCK
SS
1
PORT DATA
9
sck
Table A-18 SPI Master Mode Timing Characteristics
= 1./f
2
4
MASTER MSB OUT
5
op
MSB IN
Rating
Figure A-6 SPI Master Timing (CPHA =1)
Freescale Semiconductor, Inc.
1
For More Information On This Product,
2
6
4
2
Go to: www.freescale.com
12
11
10
BIT 6 . . . 1
BIT 6 . . . 1
LOAD
Symbol
= 200pF on all outputs
t
t
t
wsck
t
f
lead
t
t
sck
t
lag
op
t
ho
su
t
t
hi
v
r
f
11
12
MASTER LSB OUT
t
bus
Min
DC
1 2
1 2
25
LSB IN
4
0
0
30
3
Typ
1
PORT DATA
1024 t
Max
2048
1 4
25
25
25
—
bus
Unit
f
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck