MC9S12A256B ETC, MC9S12A256B Datasheet - Page 81

• Manufacturer Part Number: MC9S12A256B
• Description: device made up of standard HCS12 blocks and the HCS12 processor core
• Manufacturer: ETC

Section 6 HCS12 Core Block Description
Consult the HCS12 Core User Guide for information about the HCS12 core modules, i.e. central
processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed
external bus interface (MEBI), breakpoint module (BKP) and background debug mode module (BDM).
Section 7 Clock and Reset Generator (CRG) Block
Description
Consult the CRG Block User Guide for information about the Clock and Reset Generator module.
7.1 Device-specific information
7.1.1 XCLKS
The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).
Section 8 Enhanced Capture Timer (ECT) Block
Description
Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module.
Section 9 Analog to Digital Converter (ATD) Block
Description
There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP256B.
Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter
module.
PPAGE_SMOD_ONLY
PUCR_RESET
INITEE_WOK
INITEE_RST
NUM_INT
Name
INITEE Write anytime in normal mode
PPAGE Write only in special mode
Table 6-1 Configuration of HCS12 Core
Freescale Semiconductor, Inc.
Interrupt Request Bus Width
For More Information On This Product,
INITEE reset state
PUCR reset state
Description
Go to: www.freescale.com
MC9S12DP256B Device User Guide — V02.14
modes,reset state of the PPAGE register is
INITEE register is writeable once in
MC9S12DP256B Configuration
PPAGE register is writable in all
normal modes
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