M37754 Mitsubishi, M37754 Datasheet - Page 18

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M37754

Manufacturer Part Number
M37754
Description
SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
Manufacturer
Mitsubishi
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M37754S4CGP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
____
INTERRUPTS
Table 2 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and is
discussed in this section, too.
___
DBC is an interrupt used during debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 3 shows the
addresses of the interrupt control registers and Figure 10 shows the
bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than DBC and watchdog timer can be cleared by software.
INT
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
In the INT
to KI
trol register.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused simul-
taneously is partially fixed by hardware, but, it can also be adjusted
by software as shown in Figure 11.
The hardware priority is fixed as the following:
reset > DBC > watchdog timer > other interrupts
Fig. 10 Interrupt control register bit configuration
18
__
4
0
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2.
Note 1: The A-D conversion interrupt request bit becomes undefined after reset. Clear this bit to “0” before use of the A-D conversion interrupt.
to INT
Interrupt control register configuration for INT
Note 2: The contents of INT
7
7
___
inputs can be selected with bits 7 and 6 of INT
___
___
6
6
3
0
external interrupt, the INT
5
5
Figure 15) is set to “1.”
are external interrupts; whether to cause an interrupt at
___
4
4
3
3
2
2
1
1
___
0
0
4
interrupt control register after reset cannot be changed unless bit 5 of the particular function select register 1 (see
___
Interrupt priority level
Interrupt request bit (Note 1)
Interrupt priority level
Interrupt request bit
Polarity select bit
Level/Edge select bit
Key input interrupt select bits 1, 0 (only for INT
0 0 : INT
0 1 : Do not select.
1 0 : Key input interrupt (KI
1 1 : Key input interrupt (KI
0 : No interrupt
1 : Interrupt
0 : No interrupt
1 : Interrupt
0 : Set interrupt request bit at “H” level for level sense and when changing from “H” to “L”
1 : Set interrupt request bit at “L” level for level sense and when changing from “L” to “H”
0 : Edge sense
1 : Level sense
3
input, KI
level for edge sense.
level for edge sense.
3
interrupt selected
4
__
– INT
3
to KI
____
0
__
(Note 2).
3
0
M37754M8C-XXXGP, M37754M8C-XXXHP
interrupt con-
inputs, or KI
3
4
to KI
to KI
0
0
) selected
) selected
__
4
Table 2. Interrupt types and the interrupt vector addresses
____
____
____
____
____
____
INT
INT
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
Watchdog timer
DBC (Do not select.)
Break instruction
Zero divide
Reset
3
M37754S4CGP, M37754S4CHP
interrupt control register)
4
3
2
1
0
external interrupt
external interrupt
external interrupt
external interrupt
external interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
MITSUBISHI MICROCOMPUTERS
00FFD2
00FFD4
00FFD6
00FFD8
00FFDA
00FFDC
00FFDE
00FFE0
00FFE2
00FFE4
00FFE6
00FFE8
00FFEA
00FFEC
00FFEE
00FFF0
00FFF2
00FFF4
00FFF6
00FFF8
00FFFA
00FFFC
00FFFE
Vector addresses
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
00FFD3
00FFD5
00FFD7
00FFD9
00FFDB
00FFDD
00FFDF
00FFE1
00FFE3
00FFE5
00FFE7
00FFE9
00FFEB
00FFED
00FFEF
00FFF1
00FFF3
00FFF5
00FFF7
00FFF9
00FFFB
00FFFD
00FFFF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16

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