M37754 Mitsubishi, M37754 Datasheet - Page 21

• Manufacturer Part Number: M37754
• Description: SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

Fig. 14 Processor mode register 0 bit configuration
Fig. 15 Processor mode register 0 bit configuration
7
Notes 1: Bits 2, 3, and 4 can be re-write after bit 5 (expansion function select bit) is set to “1.”
6
2: After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset.
3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7.
5
4
7
3
Note: When selecting low-speed running, set bit 2 to “0.”
6
0
2
TC
5
1
1
TC
4
0
0
3
Particular function select register 1 (6D
Signal output stop select bit (Note 1)
Refer to Table 8.
Expansion function select bit (Note 2)
Refer to Figure 62.
Pull-up select bit 0 (Note 3)
0 : With no pull-up for P5
1 : With pull-up for P5
Pull-up select bit 1 (Note 3)
0 : With no pull-up for P9
1 : With pull-up for P9
Watchdog timer’s clock select bit (Note 1)
0 : Exclusive clock deviding circuit output (Wf
1 : Clock for peripheral device deviding circuit output (Pf
Transmit clock output pin select bit
00 : Normal mode (output only to CLK
01 : Plural clocks specified; output to CLK
10 : Plural clocks specified; output to CLKS
11 : Plural clocks specified; output to CLKS
Internal clock stop select bit at WIT (Note 1)
0 : Clock for peripheral function and watchdog timer are operating at WIT
1 : Internal clock except that for oscillation circuit and watchdog timer are stopped at WIT
2
timer. Clock (Wf
watchdog timer. Clock (Pf
Watchdog timer exclusive clock dividing circuit is stopped.
1
M37754M8C-XXXGP, M37754M8C-XXXHP
0
Processor mode register 0 (5E
Processor mode bits
00 : Single-chip mode
01 : Memory expansion mode
10 : Microprocessor mode
11 : Do not select.
Internal memory access bus cycle select bit (Note)
Software reset bit
Interrupt priority detection time select bit
0 0 : Select 0 in Figure 13
0 1 : Select 1 in Figure 13
1 0 : Select 2 in Figure 13
Test mode bit
Clock
512
Internal memory access condition in high-speed running
0 : 2- access for internal RAM, 3- access for internal ROM and SFR
1 : 2- access for internal RAM, internal ROM, SFR
0 : No
1 :
The microcomputer is reset when this bit is set to “1”.
This bit must be “0.”
, Wf
7
5
, P5
1
7
5
output
1
32
, P5
1
6
output select bit
) for watchdog timer does not change in hold.
, P5
output
512
6
, P5
, Pf
5
, P5
32
M37754S4CGP, M37754S4CHP
5
, P5
) for watchdog timer changes in hold.
4
16
0
)
)
4
0
0
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
512
, Wf
16
)
32
) is used as clock for watchdog
512
MITSUBISHI MICROCOMPUTERS
, Pf
32
) is used as clock for
21