M37754 Mitsubishi, M37754 Datasheet - Page 19

• Manufacturer Part Number: M37754
• Description: SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

Table 3. Addresses of interrupt control registers
Interrupts caused by a BRK instruction and when dividing by zero are
software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang-
ing the priority level in the corresponding interrupt control register by
software.
Figure 12 shows a diagram of the interrupt priority detection circuit
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the pri-
orities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset, DBC,
and watchdog timer interrupts are not affected by the interrupt dis-
able flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction in-
terrupts, which do not have an interrupt control register, the proces-
sor interrupt level (IPL) is set as shown in Table 4.
____
____
____
____
____
INT
INT
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
INT
INT
4
3
0
1
2
interrupt control register
interrupt control register
interrupt control register
interrupt control register
interrupt control register
Interrupt control registers
___
Addresses
00006E
00007A
00007B
00007C
00007D
00007E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007F
M37754M8C-XXXGP, M37754M8C-XXXHP
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
___
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while
until the cycles whose number is selected by software has passed,
even if the next operation code fetch cycle is generated. The detec-
tion of an interrupt which has the highest priority is performed during
that time.
Fig. 11 Interrupt priority
Fig. 12 Interrupt priority detection
A-D converter, UART, etc. interrupts
Priority can be changed with software inside 4
M37754S4CGP, M37754S4CHP
Watchdog timer
Interrupt disable flag I
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
DBC
IPL
BIU
is “H”. However, no sampling pulse is generated
MITSUBISHI MICROCOMPUTERS
Interrupt request
4
Priority is determined by hardware
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Watchdog
timer
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
3
INT
INT
INT
INT
INT
INT
INT
A-D
4
3
2
2
1
1
0
DBC
2
Level 0
Reset
1
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