M37754 Mitsubishi, M37754 Datasheet - Page 70

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M37754

Manufacturer Part Number
M37754
Description
SINGLE-CHIP 16BIT CMOS MICROCOMPUTER
Manufacturer
Mitsubishi
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M37754S4CGP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bus cycle in WIT/STP
When the WIT/STP instruction is executed with the standby state se-
lect bit 1 (bit 6 of particular function select register 0) = “0”, the clock
sources
completion of the bus cycle being executed. Accordingly, the micro-
computer may enter WIT/STP state during bus access in which out-
put of pins E, RD and WR is “L”.
Otherwise, when the WIT/STP instruction is executed with the
standby state select bit 1 = “1”, the clock sources
oscillation stop after completion of read or write in the bus access
cycle being executed. Consequently, in WIT/STP state, the bus be-
comes the nonaccess state in which output of pins E, RD and WR is
“H”.
Bus state in WIT/STP
Normally, pins for the address output, data input/output and bus
control signal output in the memory expansion/microprocessor mode
(ports P0 to P3, P10, P11 in single-chip mode; refer to section on
Processor mode) retain the state as external bus pins when the
clock sources
However, when the WIT/STP instruction is executed with the
standby state select bit 0 (bit 5 of particular function select register
0) = “1”, those pins function depending on the contents of each port
Table 8 Signal output disable select bit function (bit 4 of particular function select register 1; Figure 62)
Note : All functions of signal output disable select bit cannot be debugged using an debugger.
70
Memory expansion mode
Microprocessor mode
Microprocessor mode
Single-chip mode
Processor mode
_ ___
BIU
and
BIU
and
___
CPU
CPU
or oscillation stop without waiting for
___ ___
___
_ ___
E/RD
RD, WR
RD
ALE
stop in WIT/STP state.
1
Pin
Outputs enable signal E.
Outputs RD/WR when accessing internal/
external memory area.
Outputs “H” or “L” after executing WIT/STP
instruction
Outputs “H” when standby state select bit 1 is
“1”.
Outputs ALE.
Outputs clock
select bit.
_ ___
Signal output disable select bit = “0”
BIU
___ ___
M37754M8C-XXXGP, M37754M8C-XXXHP
and
CPU
___
1
regardless of
or
_
direction register and port latch in WIT/STP state like ports in single-
chip mode. That is, when setting arbitrary data to the port latch and
the contents of direction register to “1”, that data is output from the
pin; when clearing the contents of direction register to “0”, the pin
becomes floating. This function makes the external bus arbitrary
state in WIT/STP state. When making pins floating, take consider-
ation with an external circuit to prevent their electric potential from
becoming half level of the electric potential.
When writing to registers relevant to ports P0 to P3, P10, P11 in the
memory expansion/microprocessor mode, set the standby state se-
lect bit 0 to “1” before that write. If that bit is “0”, write is impossible,
because addresses corresponding to registers relevant to ports P0
to P3, P10, P11, which are addresses 2
the external memory areas shown in Figure 86.
[Note]
Port P11 functions as an input/output port regardless of processor
modes when inputting “L” to the BYTE pin.
The RD pin state can arbitrarily be selected in WIT/STP state in the
memory expansion/microprocessor mode, too. Refer to the Table 8
for details.
Note that the function of arbitrary data output cannot be emulated
using a debugger.
M37754S4CGP, M37754S4CHP
___
1
output
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function
Outputs “L”.
Outputs RD/WR when accessing external
memory area only.
Outputs “H” or “L” after executing WIT/STP
instruction.
Outputs “L” when standby state select bit 0 is
“1”.
Outputs “H” when standby state select bit 1 is
“1” and standby state select bit 0 is “0.”
Outputs “L” when multiplex bus select bit =
“0”.
Outputs ALE when multiplex bus select bit =
“1”.
Outputs contents of port P4
to set its direction register bit to “1”.
MITSUBISHI MICROCOMPUTERS
Signal output disable select bit = “1”
___ ___
16
to 9
16
2
, 16
latch; necessary
16
to 19
16
, are

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