MACH5 Lattice, MACH5 Datasheet - Page 2

• Manufacturer Part Number: MACH5
• Description: Fifth Generation MACH Architecture
• Manufacturer: Lattice

Note:
1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
2. Preliminary specifications for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.
GENERAL DESCRIPTION
The MACH
Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds
at high CPLD densities, low power, and supports additional features such as in-system
programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH
5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E
technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The
5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification .
2
Supply Voltage (V)
Macrocells
Maximum User I/O Pins
t
t
t
f
Typical Static Power (mA)
IEEE 1149.1 Boundary Scan Compliant
PCI-Compliant
PD
SS
COS
CNT
(ns)
(ns)
(ns)
(MHz)
®
Feature
5 family consists of a broad range of high-density and high-I/O Complex
128
120
182
5.5
3.0
4.5
Yes
Yes
35
M5LV-128
5
M5-128/1
Table 1. MACH 5 Device Features
128
120
182
3.3
5.5
3.0
4.5
Yes
Yes
35
M5-192/1
MACH 5 Family
192
120
182
5.5
3.0
4.5
Yes
Yes
45
5
256
160
182
5.5
3.0
4.5
Yes
Yes
55
M5-256/1
M5LV-256
5
256
160
182
3.3
5.5
3.0
4.5
Yes
Yes
55
167
6.5
3.0
5.0
320
192
Yes
Yes
70
1
5
M5LV-320
M5-320
2
2
2
2
167
6.5
3.0
5.0
320
192
Yes
Yes
3.3
70
2
2
2
2
167
6.5
3.0
5.0
384
160
Yes
Yes
75
5
M5LV-384
2
M5-384
2
2
2
CMOS process
2
167
6.5
3.0
5.0
384
192
3.3
Yes
Yes
75
2
2
2
2
167
6.5
3.0
5.0
512
256
100
Yes
Yes
5
M5LV-512
M5-512
2
2
2
2
167
6.5
3.0
5.0
512
256
100
3.3
Yes
Yes
2
2
2
2