MACH5 Lattice, MACH5 Datasheet - Page 30

• Manufacturer Part Number: MACH5
• Description: Fifth Generation MACH Architecture
• Manufacturer: Lattice

100-PIN TQFP CONNECTION DIAGRAM – 74 I/O
Top View
30
Pin Designations
CLK
GND = Ground
I
I/O
NC
1B11
1B12
1B13
1A14
0A14
0B13
0B12
0B11
M5LV-128
1B2
1B3
1B4
1B7
1B8
M5LV-128
0B8
0B7
0B4
0B3
0B2
= Clock
= Input
= Input/Output
= No Connect
1B11
1B12
1B13
1A12
M5LV-256
0A12
0B13
0B12
0B11
M5LV-256
1B2
1B3
1B4
1B7
1B8
0B8
0B7
0B4
0B3
0B2
I0/CLK0
I1/CLK1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
GND
GND
TCK
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
V
TDI
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
TDI
TCK
TMS
TDO = Test Data Out
CC
= Supply Voltage
= Test Data In
= Test Clock
= Test Mode Select
100-Pin TQFP (74 I/O)
MACH 5 Family
3
D
15
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Macrocell (0-15)
PAL Block (A-D)
Segment (0-3)
GND
TDO
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I/O47
I/O46
I3/CLK3
GND
V
I2/CLK2
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I/O39
I/O38
I/O37
TMS
CC
M5LV-256
M5LV-256
2B2
2B3
2B4
2B7
2B8
2B11
2B12
2B13
2A12
3A12
3B13
3B12
3B11
3B8
3B7
3B4
3B3
3B2
M5LV-128
M5LV-128
20446G-018
1C2
1C3
1C4
1C7
1C8
1C11
1C12
1C13
1D14
0D14
0C13
0C12
0C11
0C8
0C7
0C4
0C3
0C2