MACH5 Lattice, MACH5 Datasheet - Page 7

• Manufacturer Part Number: MACH5
• Description: Fifth Generation MACH Architecture
• Manufacturer: Lattice

Clock Line 1 Options
Clock Line 2 Options
Clock Line 3 Options
The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for
the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all.
All three lines can be configured for product term set/reset and two of the three lines can be
configured as sum term set/reset and one of the lines can be configured as product-term or sum-
term latch enable. While the set/reset signals are generated in the control generator, whether that
signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can
set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells
configured as latches.
PINCLK (0:3)
PT (0:3)
Global clock (0, 1, 2, or 3) with positive edge clock enable
Global clock (0, 1, 2, or 3) with negative edge clock enable
Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Global clock (0, 1, 2, or 3) with clock enable
Complement of clock line 2 (same clock enable)
Product-term clock (if clock line 2 does not use clock enable
0
1
2
3
0
1
2
3
0
1
2
3
IN (0)
IN (1)
IN (2)
IN (3)
IN (0)
IN (1)
IN (2)
IN (3)
IN (0)
IN (1)
IN (2)
IN (3)
F0
F0
MUX 4TO1
F0
MUX 4TO1
MUX 4TO1
U1
U2
U3
Figure 4. Clock Generator
OUT
OUT
OUT
F1
F1
F1
PT0
PT1
PT2
PT3
2TO1
MUX
Clock Enable
CLKIN
/CLK
CLK
CLKEN1
BIPHASE
CLKEN2
20446G-004
OUT
Clock Enable
CLKIN
MUX 2TO1
N (0)
N (1)
F0
OUT
MACH 5 Family
PTCLK
MUX 2TO1
/CLK2
F0
/CLK
MUX 2TO1
F0
CLK2
CLK1
CLK3
CLK0
Block
Clocks
0–3
PT (0:2)
Figure 5. Set/Reset Generator
PT0
PT1
PT2
/PT1(ST)
PT2
/PT2
MUX 2TO1
PT1
MUX 2TO1
F0
F0
OUT
OUT
SET2/RST2/LE
SET0/RST0
SET1/RST1
20446G-005
Block
Sets/Reset
0–2, LE
7