AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 18

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

L = Logic Low = V
Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.
Asynchronous Read Operation (Non-
Burst)
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE#
is the power control and should be used for device
selection. OE# is the output control and should be
used to gate data to the output pins if the device is
selected. The device is power-up in an asynchronous
read mode. In the asynchronous mode the device
has two control functions which must be satisfied in
order to obtain data at the outputs. CE# is the power
6. Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
16
Manufacturer ID:
AMD
PPB Protection
Status
Description
IND/WAIT#
DQ0-DQ31
Read Cycle 1
Read Cycle 2
Read Cycle 3
A0-A18
ADV#
WE#
OE#
CE#
CLK
Table 5. Am29BDD160 Autoselect Codes (High Voltage Method)
IL
, H = Logic High = V
CE#
L
L
L
L
L
OE#
L
L
L
L
L
Figure 1. Asynchronous Read Operation
WE#
H
H
H
H
H
IH
, SA = Sector Address, X = Don’t care.
A18
A11
SA
to
X
X
X
X
A10
Am29BDD160G
X
X
X
X
X
V
V
V
V
V
A9
IO
IO
IO
IO
IO
A8
X
X
X
X
X
control
OE# is the output control and should be used to gate
data to the output pins if the device is selected.
Address access time (t
stable addresses to valid output data. The chip en-
able access time (t
addresses and stable CE# to valid data at the output
pins. The output enable access time is the delay
from the falling edge of OE# to valid data at the out-
put pins (assuming the addresses have been stable
for at least t
A7
X
L
L
L
L
and should be used for device selection.
A6
L
L
L
L
L
ACC
A5
A4
to
X
X
L
L
L
–t
OE
A3
H
H
X
L
L
CE
time).
) is the delay from the stable
ACC
A2
X
H
H
L
L
) is equal to the delay from
A1
H
H
H
L
L
A0
H
H
L
L
L
0001h (bottom
(unprotected)
DQ7 to DQ0
(protected)
0000h (top
boot block)
boot block)
0001h
007Eh
0008h
0000h
0001h