AM29BDD160G AMD [Advanced Micro Devices], AM29BDD160G Datasheet - Page 28

• Manufacturer Part Number: AM29BDD160G
• Description: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile
bit that reflects the state of the Password Mode Lock-
ing Bit after power-up reset. If the Password Mode
Locking Bit is set, which indicates the device is in
Password Protection Mode, the PPB Lock Bit is also
set after a hardware reset (RESET# asserted) or a
power-up reset. The ONLY means for clearing the
PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution
of the Password Unlock command clears the PPB
Lock Bit, allowing for sector PPBs modifications. As-
serting RESET#, taking the device through a power-
on reset, or issuing the PPB Lock Bit Set command
sets the PPB Lock Bit back to a “1”.
If the Password Mode Locking Bit is not set, indicat-
ing Persistent Sector Protection Mode, the PPB Lock
Bit is cleared after power-up or hardware reset. The
PPB Lock Bit is set by issuing the PPB Lock Bit Set
command. Once set the only means for clearing the
PPB Lock Bit is by issuing a hardware or power-up
reset. The Password Unlock command is ignored in
Persistent Sector Protection Mode.
Hardware Data Protection
The command sequence requirement of unlock
cycles for programming or erasing provides
data protection against inadvertent writes. In
addition, the following hardware data protec-
tion measures prevent accidental erasure or
p ro g ram m i ng, w hi c h m ig h t o th e rwi se b e
caused by spurious system level signals during
V
from system noise.
Low V
When V
accept any write cycles. This protects data dur-
i n g V
26
(Note 2)
CC
Bank 1
power-up and power-down transitions, or
C C
CC
CC
Write Inhibit
p o w e r - u p a n d p o w e r - d o w n . T h e
Table 12. Sector Addressees for Top Boot Sector Devices (Sheet 1 of 2)
is less than V
SA0 (Note 1)
Sector
SA10
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
LKO
, the device does not
Sector Group
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
Am29BDD160G
x16 Address Range
00000h-00FFFh
01000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-04FFFh
05000h-05FFFh
06000h-06FFFh
07000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
(A18:A-1)
command register and all internal erase/pro-
gram circuits are disabled, and the device
resets. Subsequent writes are ignored until V
is greater than V
the proper signals to the control pins to prevent
unintentional writes when V
V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#,
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE# = V
a write cycle, CE# and WE# must be a logical
zero (V
Power-Up Write Inhibit
If WE# = CE# = V
power-up, the device does not accept com-
mands on the rising edge of WE#. The internal
state machine is automatically reset to reading
array data on power-up.
V
Sequencing
The device imposes no restrictions on V
V
serting RESET# to V
entire V
s p e c t i v e s u p p l i e s r e a c h t h e i r o p e ra t i n g
voltages. Once, V
ti ve o pe ra t in g vo lt a ge s , de - a s s e r ti o n o f
RESET# to V
LKO
IO
CC
power-up or power-down sequencing. As-
.
and V
IL
CC
) while OE# is a logical one (V
IL
, CE# = V
IO
and V
x32 Address Range
Power-up And Power-down
IH
00000h-007FFh
01000h-017FFh
02000h-027FFh
03000h-037FFh
00800h-00FFFh
01800h-01FFFh
02800h-02FFFh
03800h-03FFFh
04000h-07FFFh
08000h-0BFFFh
0C000h-0FFFFh
is permitted.
IO
(A18:A0)
LKO
CC
power sequence until the re-
. The system must provide
IH
and V
I L
, or WE# = V
IL
and OE# = V
is required during the
IO
attain their respec-
CC
is greater than
Sector Size
IH
(Kwords)
. To initiate
I H
32
32
32
IH
4
4
4
4
4
4
4
4
).
during
CC
and
CC