GS8160F36BT-5.5V GSI [GSI Technology], GS8160F36BT-5.5V Datasheet

GS8160F36BT-5.5V

Manufacturer Part Number

GS8160F36BT-5.5V

Description

1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8160F36BT-5.5V.pdf (21 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• Flow Through mode operation; Pin 14 = No Connect

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS8160FxxBT-xxxV is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.01 5/2006

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/21

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Designing For Compatibility

The JEDEC standard for Burst RAMS calls for a FT mode pin

option on Pin 14. Board sites for flow through Burst RAMS

should be designed with V

to ensure the broadest access to multiple vendor sources.

Boards designed with FT pin pads tied low may be stuffed with

GSI’s pipeline/flow through-configurable Burst RAMs or any

vendor’s flow through or configurable Burst SRAM. Boards

designed with the FT pin location tied high or floating must

employ a non-configurable flow through Burst RAM, like this

RAM, to achieve flow through functionality.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160FxxBT-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 1.8 V or 2.5 V compatible. Separate

output power (V

from the internal circuits and are 1.8 V or 2.5 V compatible.

-5.5

210

240

5.5

-6.5

185

205

6.5

DDQ

-7.5

170

190

7.5

) pins are used to decouple output noise

Unit

connected to the FT pin location

GS8160FxxBT-xxxV

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Preliminary

5.5 ns–8.5 ns

Related parts for GS8160F36BT-5.5V

GS8160F36BT-5.5V Summary of contents

Page 1

TQFP Commercial Temp Industrial Temp Features • Flow Through mode operation; Pin Connect • 1 2.5 V core power supply • 1 2.5 V I/O supply • LBO pin for Linear or ...

... DQP Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160F36BT-xxxV 100-Pin TQFP Pinout 512K x 36 Top View 4/21 Preliminary GS8160FxxBT-xxxV DQP ...

Page 5

TQFP Pin Description Symbol Type I — ...

Page 6

Page 7

Mode Pin Functions Mode Name Burst Order Control Power Down Control Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in ...

Page 8

Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...

Page 9

Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...

Page 10

Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B trol ...

Page 11

Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...

Page 12

Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...

Page 13

V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...

Page 14

AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...

Page 15

Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...

Page 16

Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...

Page 17

Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...

Page 18

TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...

Page 19

... Part Number GS8160F18BT-5. GS8160F18BT-6. GS8160F18BT-7.5V 512K x 32 GS8160F32BT-5.5V 512K x 32 GS8160F32BT-6.5V 512K x 32 GS8160F32BT-7.5V 512K x 36 GS8160F36BT-5.5V 512K x 36 GS8160F36BT-6.5V 512K x 36 GS8160F36BT-7. GS8160F18BT-5.5IV GS8160F18BT-6.5IV GS8160F18BT-7.5IV 512K x 32 GS8160F32BT-5.5IV 512K x 32 GS8160F32BT-6 ...

Page 20

Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number 512K x 36 GS8160F36BGT-5.5V 512K x 36 GS8160F36BGT-6.5V 512K x 36 GS8160F36BGT-7. GS8160F18BGT-5.5IV GS8160F18BGT-6.5IV GS8160F18BGT-7.5IV 512K x 32 GS8160F32BGT-5.5IV ...

Page 21

Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS8160FVxxB_r1 GS8160FVxxB_r1; GS8160FxxB-xxxV_r_01 Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Types of Changes Format or Content • Creation of new datasheet ...

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GS8160F36BT-5.5V GSI [GSI Technology], GS8160F36BT-5.5V Datasheet

GS8160F36BT-5.5V

Related parts for GS8160F36BT-5.5V

GS8160F36BT-5.5V Summary of contents

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