GS8160F36BT-5.5V GSI [GSI Technology], GS8160F36BT-5.5V Datasheet - Page 7
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GS8160F36BT-5.5V
Manufacturer Part Number
GS8160F36BT-5.5V
Description
1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8160F36BT-5.5V.pdf
(21 pages)
Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above table.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.01 5/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
10
11
00
01
00
01
10
11
Pin Name
7/21
LBO
ZZ
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
3rd address
4th address
1st address
L or NC
State
H
H
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Linear Burst
Function
Active
GS8160FxxBT-xxxV
10
00
01
11
DD
© 2004, GSI Technology
= I
SB
Preliminary
11
10
01
00
BPR 1999.05.18