GS8160Z18BT-200V GSI [GSI Technology], GS8160Z18BT-200V Datasheet
GS8160Z18BT-200V
Related parts for GS8160Z18BT-200V
GS8160Z18BT-200V Summary of contents
Page 1
Pipelined and Flow Through 100-Pin TQFP Commercial Temp Industrial Temp Features • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 1.8 ...
Page 2
... DDQ Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18BT-xxxV Pinout Top View 2/22 Preliminary GS8160ZxxBT-xxxV ...
Page 3
DQP DDQ ...
Page 4
TQFP Pin Descriptions Symbol Type ...
Page 5
GS8160V18/36BT-xxxV NBT SRAM Functional Block Diagram Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Amps Sense Drivers Write 5/22 Preliminary GS8160ZxxBT-xxxV © 2004, GSI Technology ...
Page 6
Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in ...
Page 7
Synchronous Truth Table Operation Type Address CK CKE ADV Read Cycle, Begin Burst R Read Cycle, Continue Burst B NOP/Read, Begin Burst R Dummy Read, Continue Burst B Write Cycle, Begin Burst W Write Cycle, Continue Burst ...
Page 8
Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
Page 9
Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.01 5/2006 Specifications cited are subject to change without notice. ...
Page 10
B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see ...
Page 11
Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address ...
Page 12
Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, ...
Page 13
Absolute Maximum Ratings (All voltages reference Symbol Voltage on V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
Page 14
V & V Range Logic Levels DDQ2 DDQ1 Parameter V Input High Voltage DD V Input Low Voltage DD Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions ...
Page 15
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 16
Operating Currents Parameter Test Conditions Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open Standby ZZ ≥ V – 0 Current Device Deselected; Deselect All other inputs Current ≥ ≤ ...
Page 17
AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
Page 18
Write A Write CKE ADV A0–An DQa–DQd G *Note High(False ...
Page 19
Write A Write CKE ADV A0– D(A) G *Note High(False ...
Page 20
TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
Page 21
... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8160Z18BT-250V GS8160Z18BT-200V GS8160Z18BT-150V 512K x 36 GS8160Z36BT-250V 512K x 36 GS8160Z36BT-200V 512K x 36 GS8160Z36BT-150V GS8160Z18BT-250IV GS8160Z18BT-200IV GS8160Z18BT-150IV 512K x 36 GS8160Z36BT-250IV 512K x 36 GS8160Z36BT-200IV 512K x 36 GS8160Z36BT-150IV ...
Page 22
Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8160ZVxxB_r1 8160ZVxxB_r1; 8160ZxxB_V_r_01 Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new ...