GS816218 GSI [GSI Technology], GS816218 Datasheet - Page 6

• Manufacturer Part Number: GS816218
• Description: 1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.0 9/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
FLXDrive Output Impedance Control
Single/Dual Cycle Deselect Control
2nd address
1st address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
Name
10
00
01
11
SCD
Pin
LBO
ZQ
FT
ZZ
11
00
01
10
H or NC
H or NC
H or NC
L or NC
State
H
H
L
L
L
L
6/31
High Drive (Low Impedance)
Low Drive (High Impedance)
Single Cycle Deselect
Dual Cycle Deselect
Standby, I
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
Flow Through
Linear Burst
Function
2nd address
1st address
3rd address
4th address
Pipeline
Active
DD
= I
SB
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
10
00
01
11
© 2004, GSI Technology
GS816218/36BB
Preliminary
11
10
01
00
BPR 1999.05.18