EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 2

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

EVAL-AD1896EB
The following section highlights key jumpers and switches on
the evaluation board. Please refer to the AD1896 evaluation
board schematic for more details. These switches and jumpers
configure the AD1896 and other components, such as, SPDIF
receiver, transmitter, and stereo DAC.
SWITCH AND JUMPER FUNCTIONS
• S1 is used to switch the mux inside the PLD (U2) between
• S2 selects between the RCA SPDIF input (J1) and the
• S3 is used to select the different input interface format of
• S4 selects the master/slave mode of the input and output
• S5 resets the AD1896 and other components.
• S6 activates the BYPASS function of the AD1896 where the
• S7 is used to MUTE the AD1896 output serial data as well
• S8 selects between SHORT or LONG group delay for the
• JP1 jumper is used to select output interface format and
SHARC
the Digital Interface Receiver (DIR), the CS8414 (U1), and
the Direct Digital Input (DDI HDR3) signals. The selected
signal is sourced to the input serial port of the AD1896. DIR
selection works in conjunction with the Switch S2 as
described below.
TOSLINK optical input (U4). The selected signal is
sourced to SPDIF receiver and recovered SCLK_I,
LRCLK_I, and SDATA_I signals drive the input serial
port of the AD1896.
the AD1896 input serial data. Total of six input serial modes
are possible: LJ, I
to the Digital Audio Input Signals section for the configura-
tion Table IV. Note that the input logic PLD (U2) reads
the S3 selection and controls the AD1896 and SPDIF receiver
CS8414 accordingly.
serial ports of the AD1896. Refer to Table II for the mode
selection settings. In the slave operation, the corresponding
SCLK and LRCLK signals are externally provided by the
target system. In the master mode, these two signals are
internally generated from the MCLK_I signal at 768 × f
512 × f
maximum sample rate for MASTER PORT is limited to 96 kHz.
input serial data is bypassed to the output serial port without
any signal processing.
as the AD1852 stereo DAC.
AD1896.
word width of the AD1896 output serial data. Refer to the
Digital Audio Output Signals section for configuration
Tables V and VI. Again, the output logic PLD (U3) decodes
the JP1 signals and configures the AD1852 DAC and
CS8404 SPDIF transmitter to match the output data format
of the AD1896.
®
is a registered trademark of Analog Devices, Inc.
S
, or 256 × f
2
S, RJ-24, RJ-20, RJ-18, and RJ-16. Refer
S
rate. In MASTER MODE operation,
S
,
• JP2 selects the internal interpolation ratio of the AD1852
• JP3 enables the autoMUTE feature where the AD1896
• JP4 jumper selects between an on-board clock oscillator
• 10-pin header HDR1(TDM_IN) is used to input the
• 10-pin header HDR2 (TDM_OUT) is used to receive the
• 10-pin header HDR3 (DDI) is used to drive the input serial
• 10-pin header HDR5 (DDO) is used to drive the output
LEDS
• DS1 (VERF) is illuminated when Validity+Error flag out-
• DS2 (PREEMP) indicates the pre-emphasized data to the
• DS3 (3.3 V) is illuminated when 3.3 V dc supply is present
• DS4 (AVDD = 5 V) is illuminated when analog supply to the
• DS5 (RIGHT channel) and DS6 (LEFT channel) DAC
• DS7 (AUDIO) is illuminated when the SPDIF receiver
stereo DAC (U12). Based on the sample rate, 8×, 4×, or 2×
interpolation could be selected. DAC should be configured
in 8×, 4×, or 2×… mode for 48 kHz, 96 kHz, or 192 kHz
sample rates, respectively.
MUTE_IN will be asserted if the MUTE_OUT output from
AD1896 is set high. The MUTE_OUT is set high when
sample rate of LRCLK_I and LRCLK_O changes.
(12.288 MHz) and on-board third order overtone crystal
oscillator (33.8688 MHz) for master clock (MCLK_I) of
the AD1896. Please refer to Table IX for the maximum
allowable sample rates for 76 × f
mode with 33.8688 MHz master clock. The on-board clock
oscillator (12.288 MHz) is enabled only for the SLAVE mode
operation of the AD1896 (Switch S4 position 7).
TDM_IN data from the SHARC
TDM_OUT data from the AD1896 to SHARC DSP board.
port signals SCLK_I, LRCLK_I, and SDATA_I in 3-wire
format from an external source.
serial port signals SCLK_O, LRCLK_O and SDATA_O in
3-wire format from an external source.
put on SPDIF receiver CS8414 goes high, indicating
problems with SPDIF receiver or missing audio signal to the
SPDIF receiver.
SPDIF receiver.
to power up the VDD_CORE of the AD1896.
stereo DAC AD1852 is present.
ZERO STATUS LEDs are illuminated when no input signal
is present to the stereo DAC AD1852 (U12).
CS8414 is receiving audio data.
S
, 512 × f

DSP board.
S
, and 256 × f
S
master