EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

//===================================================================================
MODULE
TITLE
//===================================================================================
//
//
//
//
//
// This output interface PLD (U3) decodes output interface signals of AD1896 and sources
// these signals to the DAC, DIT and external header (HDR2, HDR5).
// Signals SCLK_O, LRCLK_O, DDO_SCLK and DDO_LRCLK on the PLD are bi-directional signals.
// The direction of these signals are controlled by the MASTER_SLAVE MODE switch position
(S4).
// When the AD1896 output serial port is set in the master mode, the SCLK_O and LRCLK_O are
// generated from the AD1896 output serial port.
vided
// from the external source in the slave mode operation.
//
// PLD also decodes the Output Interface Format and data width Jumper header (JP1) and sets
// the Interface mode pins for the AD1896 ASRC, AD1852 DAC and CS8404 DIT to meet the inter-
face
// requirements of all three devices in any given mode.
//===================================================================================
LIBRARY 'MACH';
DECLARATIONS
//
"INPUTS
//
//
//IO SIGNALS
"NODES
//================================================================================
"MACROS
"OUTPUTS ========================================================================
FILE:
REVISION DATE: 03-20-01
REVISION BY:
REVISION:
DESCRIPTION:
TDI, TCK, TMS
SDATA_O
MS_MODE2, MS_MODE1, MS_MODE0 pin 42, 43, 44 istype 'com';
WDLNGTH1, WDLNGTH0
OPMODE1, OPMODE0
TDO
SMODE_O_1, SMODE_O_0
WDLNGTH_O_1, WDLNGTH_O_0
OSC_EN, SLVCLK1, SLVCLK0, DIV2_3
IDPM1, IDPM0
DDO_SDATA
SDATA_DAC_DIT
LRCLK_DAC, SCLK_DAC
FSYNC_DIT, SCLK_DIT
M2,M1,M0
TST9
SCLK_O, LRCLK_O
DDO_SCLK, DDO_LRCLK
I_SDATA, ISCLK, ILRCLK
IF_Logic DEVICE 'M4-64/32-15VC';
===========================================================================
IF_Logic
'AD1896 EVB Output Interface Logic'
1.0
Chirag Patel
pin 3 istype 'com, buffer';
pin 34 istype 'com, buffer';
pin 31,32,33 ISTYPE 'com';
output_pld.abl
pin 4, 7, 26 istype 'com';
pin 19, 18 istype 'com';
pin 29 istype 'com';
pin 9, 8 istype 'com';
pin 41, 40 istype 'com';
pin 22 istype 'com, buffer';
pin 37 istype 'com, buffer';
pin 1, 2 istype 'com, buffer';
pin 30, 25 istype 'com, buffer';
pin 21, 20 istype 'com';
pin 11, 10 istype 'com';
pin 36, 35 istype 'com, buffer';
pin 23, 24 istype 'com, buffer';
pin 14,12, 13, 15 istype 'com';
node istype 'com, buffer';
out_pld.abl
out_pld.abl
On the other hand, these signals are pro-
//JTAG I/P's
//JTAG O/P
EVAL-AD1896EB