EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

Switch
SW4
0
1
2
3
4
5
6
7
EVAL-AD1896EB
DIGITAL AUDIO OUTPUT SIGNALS
Similar to the input serial port, output serial data (SDATA_O,
SCLK_O, and LRCLK_O signals) can be accessed in three
different ways using this evaluation board.
1. Refer to Figure 8. Direct digital output header (HDR5) or,
2. SPDIF output through connector J2, which is generated by
3. RCA jack J6 and J7 provide stereo LEFT and RIGHT analog
SCLK_O and LRCLK_O signals of output serial port are
bidirectional signals. Logic levels on pins MMODE_ [2:0]
alternatively, TDM_OUT header (HDR2) can be used to
monitor the output serial data of the AD1896 (SDATA_O
signal) in the digital form. HDR5 provides LRCLK_O,
SCLK_O, and SDATA_O in 3-wire interface format;
whereas, HDR2 should be used in TDM mode to interface
the TDM output data to the SHARC DSP board.
the SPDIF transmitter CS8404. In this case, SCLK_O,
LRCLK_O, and SDATA_O from AD1896 are encoded in
the SPDIF signal. Similar to the SPDIF receiver, the output
sample rates above 96 kHz are not possible due to the
transmitter functionality. Note that SPDIF output is supported
only for the output port in 768
256
output signals from AD1852 DAC. Refer to Figure 10.
Interpolation ratio of the DAC needs to be set based on the
sample rate and set by jumper JP2. DAC analog output is
supported only when the AD1896 output port is configured in
768
(Switch S4 positions 4, 5, 6).
f
f
f
132.3 kHz
66.15 kHz
44.1 kHz
Not Used
Set Externally
Set Externally
Set Externally
Set Externally
S_OUT
S_OUT
S_IN
, 512
master mode (Switch S4 positions 4, 5, 6).
S3 Switch Position
0
1
2
3
4
5
6
7
f
S_OUT
f
Set Externally
Set Externally
Set Externally
Not Used
132.3 kHz
66.15 kHz
44.1 kHz
Set Externally
S_OUT
, and 256
f
S_OUT
, 512
f
S_OUT
Table III. Master/Slave Mode Configuration
Input Header (HDR3)
SCLK_I
Output
Output
Output
Input
Input
Input
Input
Input
Table IV. Input Interface Formats
master mode
f
S_OUT
SMODE_IN_[2:0]
2
0
0
1
1
1
1
0
0
, and
1
0
0
1
1
0
0
1
1
LRCLK_I
Output
Output
Output
Input
Input
Input
Input
Input
0
0
1
1
0
1
0
0
1
control the direction of these signals. Please refer to Table II
for the switch position S4 setting to control the Master/Slave
mode of the output serial port. The output interface mode,
such as I
SMODE_OUT_[2:0]. Also, the output port has two more pins
WLNGTH_OUT_[1:0] to set the output word width to 24, 20,
18, or 16 bits. The logic levels on SMODE_OUT_ [1:0] and
WLNGTH_OUT_ [1:0] pins allow different serial output data
formats. As shown in Tables V and VI, set the jumpers one and
two of JP1 for the word width and three and four of JP1 for the
output data format.
JP1[4:3]
00
01
10
11
JP1[2:1]
00
01
10
11
Output Header (HDR5)
SCLK_O
Input
Input
Input
Input
Output
Output
Output
Input
2
S, LJ, RJ, and TDM mode, is set by the pins
Table VI. Output Signal Word Width
WLNGTH_OUT_[1:0]
Table V. Output Interface Formats
SMODE_OUT_[1:0]
Input Interface Format
Left Justified
I
Right Justified, 24 Bits
Right Justified, 20 Bits
Right Justified, 18 Bits
Right Justified, 16 Bits
Not Used
Not Used
2
S
LRCLK_O
Input
Input
Input
Input
Output
Output
Output
Input
1
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
MCLK_I
[MHz]
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
Interface Format
Left-Justified (LJ)
I
TDM Mode
Right-Justified (RJ)
Word
24 Bits
20 Bits
18 Bits
16 Bits
2
S
Jumper
JP4 Short
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3