EVAL-AD1896EB AD [Analog Devices], EVAL-AD1896EB Datasheet - Page 20

• Manufacturer Part Number: EVAL-AD1896EB
• Description: AD1896 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board
• Manufacturer: AD [Analog Devices]

EVAL-AD1896EB
MODULE IF_Logic
TITLE
//===================================================================================
//
//
//
//
//
//
//
// This input interface PLD (U2) selects between the External Data Interface header
// (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending
// upon the SPDIF/DDI switch position (S1).
// signal source the digital audio signals, SDATA_I, SCLK_I and LRCLK_I are derived from
// the DIR output.
// generate these signals.
// signals from (HDR3) are applied to the AD1896.
// Signals SCLK_I, LRCLK_I, DDI_SCLK, DDI_LRCLK, DIR_SCLK, DIR_FSYNC on the PLD are
// bi-directional signals.
// MASTER_SLAVE MODE switch position (S4).
// master mode, the SCLK_I and LRCLK_I are generated from the AD1896 input serial port.
// On the other hand, these signals are provided from the external source in the slave mode
// operation.
// PLD also decodes the Input Interface Format Switch (S3) and sets the Interface mode pins
// for both the CS8414 DIR and the AD1896 ASRC.
//===================================================================================
LIBRARY 'MACH';
DECLARATIONS
//
"INPUTS ===========================================================================
//
to AD1896
SWITCH S3
"OUTPUTS =========================================================================
//
FOR AD1896
AD1896 ASRC
//IO SIGNALS
IO'S
SCLK IO'S FOR HDR3
AD1896 ASRC
"NODES
SDATA_I
FILE:
REVISION BY:
REVISION:
TDI, TCK, TMS
DIR_SDATA
SPDIF_DDI
RESET_LO
TDO
DIR_FSYNC, DIR_SCLK
DDI_LRCLK, DDI_SCLK
LRCLK_I, SCLK_I
REVISION DATE:
DESCRIPTION:
DDI_SDATA
RESET
MS_MODE2, MS_MODE1, MS_MODE0
IN_MODE2,IN_MODE1,IN_MODE0
M0, M1, M2, M3
SMODE_I_0, SMODE_I_1, SMODE_I_2
IF_Logic DEVICE 'M4-64/32-15VC';
'AD1896 EVB Input Interface Logic'
1.0
SPDIF receiver needs the digital data in the SPDIF format in order to
03-20-01
input_pld.abl
Chirag Patel
When the external data is the selected source the digital
The direction of these signals are controlled by the
pin 1 istype 'com';
pin 12 istype 'com';
pin 22 istype 'com';
Pin 44 istype 'com';
pin 37 istype 'com';
pin 35,36;
pin 24,25,30 istype 'com';
pin 29 istype 'com';
pin 33,32,31 istype 'com';
Pin 23 istype 'com';
pin 2,3;
pin 21,20;
pin 18,15,14 istype 'com';
pin 8,9,10,11 istype 'com'; //SPDIF_RVR MODE SELECT
in_pld.abl
pin 4,7,26 istype 'com';
When the AD1896 input serial port is set in the
When the SPDIF Receiver DIR is the selected
//EXTERNAL DATA INPUT DDI
//LRCLK_I AND SCLK_I IO'S TO
//MASTER/SLAVE MODE SWITCH S4
//Active low reset input
//SERIAL DATA INPUT TO
//INPUT SERIAL MODE FORMAT
//SPDIF_DDI SWITCH S1
//CS8414 DIR SDATA OUT
//Active hi reset output
//INPUT SERIAL MODE
//JTAG O/P
//EXTERNAL LRCLK AND
//DIR_FYSNC AND DIR_SCLK
//JTAG I/P's