AM29F002N AMD [Advanced Micro Devices], AM29F002N Datasheet - Page 7

• Manufacturer Part Number: AM29F002N
• Description: 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend:
L = Logic Low = V
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Read
TTL Standby
Output Disable
Reset (n/a on Am29F002N)
Temporary Sector Unprotect
(See Note)
Write
CMOS Standby
IH
.
Operation
IL
, H = Logic High = V
CC1
Table 1. Am29F002/Am29F002N Device Bus Operations
in the DC Characteristics
IL
. CE# is the power
IH
, V
V
CC
ID
CE#
± 0.5 V
= 12.0 0.5 V, X = Don’t Care, D
H
X
X
L
L
L
Am29F002/Am29F002N
P R E L I M I N A R Y
OE#
H
X
X
H
X
X
L
WE#
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and Autoselect
Command Sequence sections for more information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
H
X
X
H
X
X
L
CC2
in the DC Characteristics table represents the ac-
(n/a Am29F002N)
IL
, and OE# to V
IN
RESET#
= Data In, D
V
H
H
H
H
H
L
ID
OUT
IH
.
= Data Out, A
A0–A17
A
A
X
X
X
X
X
IN
IN
IN
DQ0–DQ7
= Address In
High-Z
High-Z
High-Z
High-Z
D
D
OUT
X
IN
CC
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