HY27SF161G2A HYNIX [Hynix Semiconductor], HY27SF161G2A Datasheet - Page 15

• Manufacturer Part Number: HY27SF161G2A
• Description: 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.8 Cache program
Cache Program is an extension of Page Program, which is executed with 2112byte (X8 device) or 1056word (X16
device) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data
input may be executed while data stored in data register are programmed into memory cell. After writing the first set
of data up to 2112byte (X8 device) or 1056word (X16 device) into the selected cache registers, Cache Program com-
mand (15h) instead of actual Page Program (10h) is input to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period
of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started
with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers
become ready by polling the Cache- Busy status bit (I/O 6). Pass/fail status of only the previous page is available
upon the return to Ready state.
When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending
internal programming. The programming of the cache registers is initiated only when the pending program cycle is
finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for
internal Ready/Busy may be polled to identify the completion of internal programming.
If the system monitors the progress of programming only with R/B, the last page of the target programming sequence
must be programmed with actual Page Program command (10h). If the Cache Program command (15h) is used
instead, status bit (I/O5) must be polled to find out when the last programming is actually finished before starting
other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the status of the previous
page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true Ready
(returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is
checked. See Fig. 17 for more details.
NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program.
However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page
is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG=Program time for the last page + Program time for the (last-1)page
- (Program command cycle time + Last page data loading time)
Rev 0.3 / Nov. 2006
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