HY27SF161G2A HYNIX [Hynix Semiconductor], HY27SF161G2A Datasheet - Page 16

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HY27SF161G2A

Manufacturer Part Number
HY27SF161G2A
Description
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.9 Cache Read
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page must be at page start (A<10:0>=00h) : in this way after 1st latency time (tr) , automatic
data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for
x8 device (50us for x16 device).
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
- R/B ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device in
ternally is active on n+1 page
- Status register (SR<6> behave like R/B, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
To exit cache read operation, a cache read exit command (34h) must be issued. This command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tRBSY before becoming again idle and ready to accept any further commands. Figure 21 describes how
to handle Cache Read through Status register .
If user reads last byte/word of the memory array, then he has to stop by giving a cache read exit command. In general,
if user wants to terminate a cache read, then he must give a cache read exit command (or reset command) before
starting any new operation.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.3 / Nov. 2006
16

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