EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 21

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

CONTROL PORTS
The ADAU1401 can operate in one of three control modes:
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•
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The ADAU1401 has both a 4-wire SPI control port and a
2-wire I
and registers. When the SELFBOOT pin is low at power-up, the
part defaults to I
by pulling the CLATCH/WP pin low three times. When the
SELFBOOT pin is set high at power-up, the ADAU1401 loads
its program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the param-
eter RAM using the control port. Other functions, such as mute
and input/output mode control, are programmed by writing to
the registers.
All addresses can be accessed in a single-address mode or a
burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1401. This
subaddress must be two bytes because the memory locations
Table 15. Control Port Pins and SELFBOOT Pin Functions
Pin
SCL/CCLK
SDA/COUT
ADDR1/CDATA/WB
CLATCH/WP
ADDR0
I
SPI control
Self-boot (no external controller)
2
C control
2
C bus control port. Each can be used to set the RAMs
2
C mode but can be put into SPI control mode
I
SCL—input
SDA—open-collector output
ADDR1—input
Unused input—tie to ground or IOVDD
ADDR0—input
2
C Mode
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ADDR0—input
SPI Mode
CCLK—input
COUT—output
CDATA—input
CLATCH—input
within the ADAU1401 are directly addressable and their sizes
exceed the range of single-byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in Table 23 to Table 32.
The ADAU1401 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at startup or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides the safeload registers. The safeload registers
can be used to buffer a full set of parameters (for example, the
five coefficients of a biquad) and then transfer these parameters
into the active program within one audio frame. The safeload
mode uses internal logic to prevent contention between the
DSP core and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 15 details these
multiple functions.
Self-Boot
SCL—output
SDA—open-collector output
WB—writeback trigger
WP—EEPROM write protect, open-collector output
Unused input—tie to ground or IOVDD
ADAU1401