EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 45

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

The input control register allows control of clock polarity and
data input modes. The valid data formats are I
right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all
modes except for the right-justified modes, the serial port accepts
an arbitrary number of bits up to a limit of 24. Extra bits do not
cause an error, but they are truncated internally. Proper operation
of the right-justified modes requires that there be exactly 64 BCLKs
per audio frame. The TDM data is input on SDATA_IN0. The
LRCLK in TDM mode can be input to the ADAU1401 either as
a 50/50 duty cycle clock or as a bit-wide pulse.
In TDM mode, the ADAU1401 can be a master for 48 kHz and
96 kHz data, but not for 192 kHz data. Table 65 lists the modes
in which the serial output port can function.
Table 65. Serial Output Port Master/Slave Mode Capabilities
f
48 kHz
96 kHz
192 kHz
The output control registers allow the user to control clock
polarities, clock frequencies, clock types, and data format. In all
modes except for the right-justified modes (MSB delayed by 8,
12, or 16 bits), the serial port accepts an arbitrary number of
bits up to a limit of 24. Extra bits do not cause an error, but are
truncated internally. Proper operation of the right-justified modes
requires the LSB to align with the edge of the LRCLK. The default
settings of all serial port control registers correspond to 2-channel
I
modes unless otherwise noted.
The function of each multipurpose pin in serial data port mode
is shown in Table 66. Pin MP0 to Pin MP5 support digital data
input to the ADAU1401, and Pin MP6 to Pin MP11 handle digital
data output from the DSP. The configuration of the serial data
input port is set in the serial input control register (Table 52), and
Table 67. Data Format Configurations
Format
I
Left-Justified (Figure 32)
Right-Justified (Figure 33)
TDM with Clock (Figure 34)
TDM with Pulse (Figure 35)
2
S
2
S (Figure 31)
S mode. All register settings apply to both master and slave
2-Channel Modes
(I
Right-Justified)
Master and slave
Master and slave
Master and slave
2
S, Left-Justified,
LRCLK Polarity
Frame begins on falling edge
Frame begins on rising edge
Frame begins on rising edge
Frame begins on falling edge
Frame begins on rising edge
8-Channel TDM
Master and slave
Master and slave
Slave only
2
S, left-justified,
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LRCLK
Type
Clock
Clock
Clock
Clock
Pulse
BCLK Polarity
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
the configuration of the corresponding output port is controlled
with the serial output control register (Table 50). The clocks of
the input port function only as slaves, whereas the output port
clocks can be set to function as either masters or slaves. The
INPUT_LRCLK (MP4) and INPUT_BCLK (MP5) pins are
used to clock the SDATA_INx (MP0 to MP3) signals, and the
OUTPUT_LRCLK (MP10) and OUTPUT_BCLK (MP11) pins
are used to clock the SDATA_OUTx (MP6 to MP9) signals.
If an external ADC is connected as a slave to the ADAU1401,
use both the input and output port clocks. The OUTPUT_LRCLK
(MP10) and OUTPUT_BCLK (MP11) pins must be set to master
mode and connected externally to the INPUT_LRCLK (MP4)
and INPUT_BCLK (MP5) pins as well as to the external ADC
clock input pins. The data is output from the external ADC into
the SigmaDSP on one of the four SDATA_INx pins (MP0 to MP3).
Connections to an external DAC are handled exclusively with the
output port pins. The OUTPUT_LRCLK and OUTPUT_BCLK
pins can be set to function as either masters or slaves, and the
SDATA_OUTx pins are used to output data from the SigmaDSP
to the external DAC.
Table 67 describes the proper configurations for standard audio
data formats.
Table 66. Multipurpose Pin Serial Data Port Functions
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
Function
SDATA_IN0/TDM_IN
SDATA_IN1
SDATA_IN2
SDATA_IN3
INPUT_LRCLK (slave only)
INPUT_BCLK (slave only)
SDATA_OUT0/TDM_OUT
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
OUTPUT_LRCLK (master or slave)
OUTPUT_BCLK (master or slave)
MSB Position
Delayed from LRCLK edge
by 1 BCLK
Aligned with LRCLK edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs
Delayed from start of word clock
by 1 BCLK
Delayed from start of word clock
by 1 BCLK
ADAU1401