EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

ADAU1401
I
The ADAU1401 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1401 and the system I
In I
meaning it cannot initiate a data transfer. Each slave device is
recognized by a unique address. The address byte format is
shown in Table 16. The ADAU1401 slave addresses are set with
the ADDR0 and ADDR1 pins. The address resides in the first
seven bits of the I
or write operation. Logic Level 1 corresponds to a read operation,
and Logic Level 0 corresponds to a write operation. Bit 5 and
Bit 6 of the address are set by tying the ADDRx pins of the
ADAU1401 to Logic Level 0 or Logic Level 1. The full byte
addresses, including the pin settings and read/ write bit, are
shown in Table 17.
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless a
stop condition is encountered. The registers and RAMs in the
ADAU1401 range in width from one to five bytes, so the auto-
increment feature knows the mapping between subaddresses and
the word length of the destination register (or memory location). A
data transfer is always terminated by a stop condition.
Both SDA and SCL should have 2.2 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than IOVDD (3.3 V).
Table 16. ADAU1401 I
Bit 0
0
Table 17. ADAU1401 I
ADDR1
0
0
0
0
1
1
1
1
2
C PORT
2
C mode, the ADAU1401 is always a slave on the bus,
Bit 1
1
ADDR0
0
0
1
1
0
0
1
1
Bit 2
1
2
C write. The LSB of this byte sets either a read
Read/Write
0
1
0
1
0
1
0
1
Bit 3
0
2
2
C Address Byte Format
C Addresses
Bit 4
1
Bit 5
ADDR1
2
C master controller.
2
C-compatible)
Slave Address
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
Bit 6
ADDR0
Bit 7
R/W
Rev. 0 | Page 22 of 52
Addressing
Initially, each device on the I
the SDA and SCL lines for a start condition and the proper address.
The I
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/ W bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is known as an acknowledge bit. All other
devices withdraw from the bus at this point and return to the
idle condition. The R/ W bit determines the direction of the
data. A Logic 0 on the LSB of the first byte means the master
will write information to the peripheral, whereas a Logic 1
means the master will read information from the peripheral
after writing the subaddress and repeating the start address. A
data transfer takes place until a stop condition is encountered.
A stop condition occurs when SDA transitions from low to high
while SCL is held high. Figure 20 shows the timing of an I
write, and Figure 21 shows an I
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1401 immediately
jumps to the idle condition. During a given SCL high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1401 does
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the ADAU1401
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no-acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. On the other hand, if the
highest subaddress location is reached while in write mode, the
data for the invalid byte is not loaded into any subaddress register,
a no acknowledge is issued by the ADAU1401, and the part returns
to the idle condition.
2
C master initiates a data transfer by establishing a start
2
C bus is in an idle state monitoring
2
C read.
2
C