EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

ADAU1401
DIGITAL TIMING SPECIFICATIONS
Table 8. Digital Timing
Parameter
MASTER CLOCK
SERIAL PORT
SPI PORT
I
MULTIPURPOSE PINS AND RESET
1
2
All timing specifications are given for the default (I
C PORT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MP
MP
MP
MP
BIL
BIH
LIS
LIH
SIS
SIH
LOS
LOH
TS
SODS
SODM
CCLK
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
SCL
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
GRT
GFT
GIL
RLPW
1
t
36
48
73
291
40
40
10
10
10
10
10
10
80
80
0
100
80
0
80
0.6
1.3
0.6
0.6
100
0.6
20
MIN
2
S) states of the serial input port and the serial output port (see Table 67).
Limit
t
244
366
488
1953
5
40
40
6.25
101
400
300
300
300
300
50
50
1.5 × 1/f
MAX
S
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
ns
Description
MCLKI period, 512 × f
MCLKI period, 384 × f
MCLKI period, 256 × f
MCLKI period, 64 × f
INPUT_BCLK low pulse width.
INPUT_BCLK high pulse width.
INPUT_LRCLK setup. Time to INPUT_BCLK rising.
INPUT_LRCLK hold. Time from INPUT_BCLK rising.
SDATA_INx setup. Time to INPUT_BCLK rising.
SDATA_INx hold. Time from INPUT_BCLK rising.
OUTPUT_LRCLK setup in slave mode.
OUTPUT_LRCLK hold in slave mode.
OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.
SDATA_OUTx delay in slave mode. Time from OUTPUT_BCLK falling.
SDATA_OUTx delay in master mode. Time from OUTPUT_BCLK falling.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT delay. Time from CCLK falling.
SCL frequency.
SCL high.
SCL low.
Setup time, relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
GPIO rise time.
GPIO fall time.
GPIO input latency. Time until high/low value is read by core.
RESET low pulse width.
S
S
S
S
mode.
mode.
mode.
mode.