OR3T125 Agere Systems, OR3T125 Datasheet - Page 106

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 42. Sequential PFU Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
* Four-input variables’ (K
Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same
106
Input Requirements
Clock Low Time
Clock High Time
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
Combinatorial Setup Times (T
Combinatorial Hold Times (T
Output Characteristics
Sequential Delays (T
Data In to Clock (DIN[7:0] to CLK)
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK)
Clock Enable to Clock (CE to CLK)
Clock Enable to Clock (ASWE to CLK)
Local Set/Reset to Clock (SYNC) (LSR to CLK)
Data Select to Clock (SEL to CLK)
Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Two-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Three-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Data In (DIN[7:0] from CLK)
Carry-in from Clock, DIRECT to REGCOUT (CIN from
Clock Enable (CE from CLK)
Clock Enable from Clock (ASWE from CLK)
Local Set/Reset from Clock (sync) (LSR from CLK)
Data Select from Clock (SEL from CLK)
All Others
Local S/R (async) to PFU Out (LSR to Q[7:0], REG-
Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT)
Clock to PFU Out—Register (CLK to Q[7:0], REG-
Clock to PFU Out—Latch (CLK to Q[7:0])
Transparent Latch (DIN[7:0] to Q[7:0])
Four-input Variables to Clock (Kz[3:0] to CLK)*
Five-input Variables to Clock (F5[A:D] to CLK)
CLK)
COUT)
COUT)
timing parameter and may accurately report delays that are less than those listed.
J
Z
= +85 °C, V
Parameter
[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
DD
DD
= 5.0 V ± 5%, 0 °C < T
J
= 3.0 V to 3.6 V, 0 °C < T
J
= all, V
= +85 °C, V
DD
(continued)
DD
= min):
= all):
DD
= min):
A
< 70 °C; Industrial: V
A
< 70 °C; Industrial: V
SWL2F5_SET
SWL3F5_SET
CINDIR_SET
CINDIR_HLD
LTCHD_DEL
CLKH_MPW
CLKL_MPW
SWL2_SET
SWL3_SET
GSR_MPW
LTCH_DEL
LSR_MPW
GSR_DEL
REG_DEL
CE1_SET
CE2_SET
LSR_SET
CE1_HLD
CE2_HLD
LSR_HLD
SEL_HLD
LSR_DEL
SEL_SET
DIN_HLD
DIN_SET
Symbol
F4_SET
F5_SET
—
Min Max Min Max Min Max Min Max
3.36
1.61
3.36
3.36
1.99
1.79
0.47
1.25
2.86
1.68
1.86
1.37
3.98
4.06
6.49
6.39
0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
DD
-4
DD
= 5.0 V ± 10%, –40 °C < T
7.02
5.21
2.38
2.51
2.73
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= 3.0 V to 3.6 V, –40 °C < T
2.07
1.06
2.07
2.07
1.47
1.33
0.32
0.99
2.15
1.30
1.36
1.00
2.99
2.97
4.81
4.73
0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
-5
5.29
3.90
1.75
1.88
2.10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Speed
Lucent Technologies Inc.
0.94
0.54
0.94
0.94
1.08
1.03
0.18
0.71
1.80
0.95
0.86
0.92
2.13
2.29
3.42
3.34
0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
-6
3.64
2.55
1.26
1.21
1.38
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
< +85 °C.
Data Sheet
0.72
0.45
0.72
0.72
0.85
0.81
0.16
0.58
1.37
0.77
0.68
0.70
1.63
1.68
2.64
2.57
0.00
0.00
0.00
0.00
0.00
0.00
0.00
June 1999
A
—
—
—
—
—
< +85 °C
-7
2.90
2.00
0.97
0.96
1.12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns