OR3T125 Agere Systems, OR3T125 Datasheet - Page 124

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Timing Characteristics
Table 53 . General-Purpose Clock Timing Characteristics (Internally Generated Clock)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
Notes:
This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on
any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the
results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not
used. See pin-to-pin timing in Table 56 for clock delays of clocks input on general I/O pins.
124
(T
J
= 85 °C, V
OR3C/T55
OR3C/T80
OR3T125
OR3T20
OR3T30
Device
DD
= min)
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
CLK_DEL
CLK_DEL
CLK_DEL
CLK_DEL
CLK_DEL
Symbol
(continued)
Min
—
—
—
—
—
<
T
-4
<
A
<
T
Max
5.34
5.49
A
—
—
—
70 °C; Industrial: V
<
70 °C; Industrial: V
Min
—
—
—
—
—
-5
Max
4.22
4.29
4.41
4.52
4.80
DD
Speed
DD
= 5.0 V ± 10%, –40 °C
= 3.0 V to 3.6 V, –40 °C
Min
—
—
—
—
—
-6
Max
3.46
3.48
3.53
3.57
3.71
Lucent Technologies Inc.
<
Min
—
—
—
—
—
T
A
<
<
-7
T
+85 °C.
A
<
Max
2.84
2.87
2.93
2.98
3.13
Data Sheet
June 1999
+85 °C.
Unit
ns
ns
ns
ns
ns