OR3T125 Agere Systems, OR3T125 Datasheet - Page 13

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Data Sheet
June 1999
Lucent Technologies Inc.
Programmable Logic Cells
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT
memory.
Table 3 lists the basic operating modes of the LUT. Figure 4—Figure 10 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for generating logic.
Table 3. Look-Up Table Operating Modes
PFU Control Inputs
Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The five control inputs are CLK, LSR, CE, ASWE, and SEL, and their
functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the
PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be
configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a
function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an
optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the
input to the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indi-
cates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple
modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble
(latch/FF[3:0], latch/FF[7:4]) and for the ninth FF.
Half Logic/
Half Ripple
Memory
Ripple
Mode
Logic
4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to
ninth FF or as pass through to COUT.
Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN
and ninth FF for logic or ripple functions.
All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in
use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode
are adder/subtractor, counter, multiplier, and comparator.
All LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as single-
port or as ROM.
(continued)
Function
ORCA Series 3C and 3T FPGAs
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