OR3T125 Agere Systems, OR3T125 Datasheet - Page 3

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

Contents
Data Sheet
June 1999
Package Coplanarity ...............................................196
Package Parasitics ..................................................196
Package Outline Diagrams......................................197
Ordering Information................................................206
Index........................................................................207
Tables
Table 1. ORCA Series 3 (3C and 3T) FPGAs ............ 2
Table 2. ORCA Series 3 System Performance .......... 6
Table 3. Look-Up Table Operating Modes ............... 13
Table 4. Control Input Functionality .......................... 14
Table 5. Ripple Mode Equality Comparator
Table 6. SLIC Modes ................................................ 21
Table 7. Configuration RAM Controlled
Table 8. Inter-PLC Routing Resources ..................... 31
Table 9. PIO Options ................................................ 37
Table 10. PIO Logic Options .................................... 43
Table 11. PIO Register Control Signals .................... 43
Table 12. Readback Options .................................... 54
Table 13. Boundary-Scan Instructions ..................... 58
Table 14. Boundary-Scan ID Code ........................... 59
Table 15. TAP Controller Input/Outputs ................... 61
Table 16. PowerPC /MPI Configuration ..................... 65
Table 17. i960 /MPI Configuration ............................. 66
Table 18. MPI Internal Interface Signals .................. 67
Table 19. MPI Setup and Control Registers ............. 68
Table 20. MPI Setup and Control Registers
Table 21. MPI Control Register 2 ............................. 69
Table 22. Status Register ......................................... 70
Table 23. Device ID Code ........................................ 71
Table 24. Series 3 Family and Device ID Values ..... 71
Table 25. ORCA Series 3 Device ID Descriptions .... 71
Table 26. PCM Registers ......................................... 73
Table 27. DLL Mode Delay/1x Duty Cycle
Table 28. DLL Mode Delay/2x Duty Cycle
Table 29. PCM Oscillator Frequency Range 3Txxx . 78
Table 30. PCM Oscillator Frequency Range 3Cxx ... 78
Table 31. PCM Control Registers ............................. 80
Lucent Technologies Inc.
Terms and Definitions ...........................................197
208-Pin SQFP .......................................................198
208-Pin SQFP2 .....................................................199
240-Pin SQFP .......................................................200
240-Pin SQFP2 .....................................................201
256-Pin PBGA .......................................................202
352-Pin PBGA .......................................................203
432-Pin EBGA .......................................................204
600-Pin EBGA .......................................................205
Functions and Outputs ............................................ 18
Latch/Flip-Flop Operation ........................................ 25
Description ............................................................... 68
Programming Values ............................................... 75
Programming Values ............................................... 76
Table of Contents
Page
Contents
Table 32. Configuration Frame Format and
Table 33. Configuration Frame Size .........................91
Table 34. Configuration Modes ................................92
Table 35. Absolute Maximum Ratings ....................100
Table 36. Recommended Operating Conditions ....100
Table 37. Electrical Characteristics ........................101
Table 38. Derating for Commercial Devices
Table 39. Derating for Industrial Devices (OR3Cxx) 103
Table 40. Derating for Commercial/Industrial
Table 41. Combinatorial PFU Timing
Table 42. Sequential PFU Timing Characteristics ..106
Table 43. Ripple Mode PFU Timing
Table 44. Synchronous Memory Write
Table 45. Synchronous Memory Read
Table 46. PFU Output MUX and Direct Routing
Table 47. Supplemental Logic and Interconnect
Table 48. Programmable I/O (PIO) Timing
Table 49. Microprocessor Interface (MPI) Timing
Table 50. Programmable Clock Manager (PCM)
Table 51. Boundary-Scan Timing Characteristics ..122
Table 52. ExpressCLK (ECLK) and Fast Clock
Table 53. General-Purpose Clock Timing
Table 54. OR3Cxx ExpressCLK to Output Delay
Table 55. OR3Cxx Fast Clock (FCLK) to Output
Table 56. OR3Cxx General System Clock (SCLK)
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK)
Table 58. OR3C/Txxx Input to Fast Clock
Table 59. OR3C/Txxx Input to General System
Table 60. General Configuration Mode Timing
Table 61. Master Serial Configuration Mode Timing
Contents ..................................................................90
(OR3Cxx) ..............................................................103
Devices (OR3Txxx) ...............................................103
Characteristics .......................................................104
Characteristics .......................................................107
Characteristics .......................................................109
Characteristics .......................................................110
Timing Characteristics ...........................................111
Cell (SLIC) Timing Characteristics ........................111
Characteristics .......................................................112
Characteristics .......................................................115
Timing Characteristics (Preliminary Information) ..121
(FCLK) Timing Characteristics ..............................123
Characteristics (Internally Generated Clock) .........124
(Pin-to-Pin) ............................................................125
Delay (Pin-to-Pin) ..................................................126
to Output Delay (Pin-to-Pin) ..................................127
Fast-Capture Setup/Hold Time (Pin-to-Pin) ..........128
Setup/Hold Time (Pin-to-Pin) ................................130
Clock (SCLK) Setup/Hold Time (Pin-to-Pin) ..........132
Characteristics .......................................................133
ORCA Series 3C and 3T FPGAs
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