OR3T125 Agere Systems, OR3T125 Datasheet - Page 60

• Manufacturer Part Number: OR3T125
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: Agere Systems

ORCA Series 3C and 3T FPGAs
Special Function Blocks
ORCA Boundary-Scan Circuitry
The ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the four pre-
defined instructions.
Figure 38 shows a functional diagram of the boundary-
scan circuitry that is implemented in the ORCA Series.
The input pins’ (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in
the BSR. The first BSC in the BSR (connected to TDI)
is located in the first PIC I/O pad on the left of the top
side of the FPGA (PTA PIC). The BSR proceeds clock-
wise around the top, right, bottom, and left sides of the
array. The last BSC in the BSR (connected to TDO) is
located on the top of the left side of the array (PL1D).
The bypass instruction uses a single FF, which resyn-
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
60
60
Figure 38. ORCA Series Boundary-Scan Circuitry Functional Diagram
PRGM
TMS
TCK
V
V
V
DD
DD
DD
(continued)
TDI
CONTROLLER
UPDATE-DR
CLOCK DR
SHIFT-DR
V
TAP
DD
RESET
DATA REGISTERS
BOUNDARY-SCAN REGISTER
CONFIGURATION REGISTER
PSR1 REGISTER (PLCs)
PSR2 REGISTER (PLCs)
PUR
INSTRUCTION DECODER
INSTRUCTION REGISTER
IDCODE REGISTER
BYPASS REGISTER
RESET
CLOCK IR
SHIFT-IR
UPDATE-IR
(RAM_R, RAM_W)
I/O BUFFERS
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not boundary-scan logic
is used.
The 32-bit boundary-scan identification register con-
tains the manufacturer’s ID number, unique part num-
ber, and version (as described earlier). The
identification register is the default source for data on
TDO after RESET if the TAP controller selects the shift-
data-register (SHIFT-DR) instruction. If boundary scan
is not used, TMS, TDI, and TCK become user I/Os,
and TDO is 3-stated or used in the readback operation.
An optional USERCODE is available if the boundary-
scan PSR1 instruction is not used. The selection
between PSR1 and USERCODE is a configuration
option and can be performed in ORCA Foundry. The
USERCODE is an 11-bit value that the user can set
during device configuration and can be written to and
read from the FPGA via the boundary-scan logic. The
USERCODE value replaces the manufacturer field of
the boundary-scan ID code when the USERCODE
instruction is issued, allowing users to have configured
devices identified in a user-defined manner. The manu-
facturer ID field remains available when the IDCODE
instruction is issued.
DATA
MUX
SELECT
ENABLE
M
U
X
TDO
Lucent Technologies Inc.
Data Sheet
June 1999
5-5768(F)