AK4632VN AKM [Asahi Kasei Microsystems], AK4632VN Datasheet - Page 51

• Manufacturer Part Number: AK4632VN
• Description: 16-Bit ?? Mono CODEC with ALC & MIC/SPK/Video-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
MS0396-E-00
Addr
07H
LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (See Table 38 )
RATT: ALC1 Recovery GAIN Step (See Table 39)
LMAT1-0: ALC1 Limiter ATT Step (See Table 40)
ZELM: Enable zero crossing detection at ALC1 Limiter operation
LMTH bit
0: Enable (Default)
1: Disable
Register Name
ALC Mode Control 1
0
1
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.
Default is “0”.
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the
ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value
exceeds the reference level (REF6-0 bits), the IPGA value does not increase.
During the ALC1 limiter operation, when IPGA output signal exceeds the ALC1 limiter detection level set by
LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current
IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter
operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation
value exceeds IPGA = “00” (−8dB), it clips to “00”.
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently
and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1
recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
Default
Table 38. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Limiter Detection Level
ADC Input ≥ −6.0dBFS
ADC Input ≥ −4.0dBFS
Table 39. ALC1 Recovery Gain Step Setting
Table 40. ALC1 Limiter ATT Step Setting
D7
0
0
LMAT1 bit
RATT bit
0
0
1
1
0
1
ALC2
D6
1
LMAT0 bit
ALC1 Recovery Waiting Counter Reset Level
- 51 -
GAIN STEP
ALC1
−6.0dBFS > ADC Input ≥ −8.0dBFS
−4.0dBFS > ADC Input ≥ −6.0dBFS
0
1
0
1
D5
0
1
2
ZELM
D4
ATT STEP
0
1
2
3
4
Default
LMAT1
D3
0
Default
LMAT0
D2
0
RATT
D1
0
Default
[AK4632]
LMTH
2005/06
D0
0