AK4632VN AKM [Asahi Kasei Microsystems], AK4632VN Datasheet - Page 62

• Manufacturer Part Number: AK4632VN
• Description: 16-Bit ?? Mono CODEC with ALC & MIC/SPK/Video-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
MS0396-E-00
DVOL7-0 bits
(Addr:0AH, D7-0)
(Addr:02H, D3)
Speaker-amp Output
(Addr:02H, D5)
(Addr:07H, D6)
(Addr:00H, D2)
(Addr:00H, D4)
(Addr:02H, D7)
<Example>
PMDAC bit
PMSPK bit
ALC2S bit
FS2-0 bits
DACM bit
SPPS bit
ALC2 bit
(Addr:05H,
SPP pin
SPN pin
D5, D2-0)
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Speaker-Amp should be
(2) Set up the path of “DAC
(3) Set up the ALC2 Enable/Disable
(4) Set up the digital volume (Addr: 0AH)
(5) Power Up of DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “0” → “1”
(6) Exit the power-save-mode of Speaker-Amp: SPPS bit = “0” → “1”
(7) Enter the power-save-mode of Speaker-Amp: SPPS bit = “1” → “0”
(8) Disable the path of “DAC
(9) Power Down DAC and Speaker-Amp: PMDAC bit = PMSPK bit = “1” → “0”
powered-up in consideration of PLL lock time after a sampling frequency is changed.
When ALC2 bit = “1”, the ALC2 is disabled (ALC2 gain is fiexed to “–2dB”) during the initilization cycle
(512/fs = 64ms @ fs=8kHz, ROTM bit = “0”) and the ALC2 starts from “–2dB” after completing the
initilization cycle.
MOUT pin. If Speaker-Amp output is enabled before MIN-Amp (ALC2) becomes stable, pop noise may occur.
“(6)” time depends on the time constant of input impedance of MIN pin and capacitor between MIN pin and
DACM = ALC2S bit: “0” → “1”
After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by
the soft transition.
DACM = ALC2S bit: “1” → “0”
e.g. Input Impedance of MIN pin =36kΩ (max), C=0.1µF: Recommended wait time is more than 5τ = 18ms.
XXXX
0001100
0
Hi-Z
(2)
Hi-Z
(1)
(3)
(4)
(5)
SVDD/2
SPK-Amp”
SPK-Amp”
Figure 51. Speaker-Amp Output Sequence
(6)
Normal Output
Normal Output
XXXX
XXXXXXX
X
- 62 -
(7)
SVDD/2
(8)
Hi-Z
(9)
Hi-Z
Example:
PLL, Master Mode
Audio I/F Format :DSP Mode, BCKP=MSBS= “0”
Sampling Frequency: 8kHz
ALC2 : Enable
Digital Volume: -8dB
(1) Addr:05H, Data:00H
(4) Addr:0AH, Data:28H
(2) Addr:02H, Data:28H
(3) Addr:07H, Data:40H
(6) Addr:02H, Data:A8H
(7) Addr:02H, Data:28H
(5) Addr:00H, Data:54H
(8) Addr:00H, Data:40H
Playback
[AK4632]
2005/06