ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet
ZL30461MGG
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ZL30461MGG Summary of contents
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... Selectable operation modes • Alarm output indication Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, 2003, Zarlink Semiconductor Inc. All Rights Reserved. Compact Stratum 3 Timing Module ZL30461MGG Applications • SONET/SDH Add/Drop multiplexers • SONET/SDH up-links • ...
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Description The ZL30461 is a Compact Timing Module, which functions as a complete system clock solution for general Stratum 3 and SONET/SDH timing applications. The ZL30461 uses Zarlink's Digital and Analog Phase Locked Loop (DPLL and APLL) technology and can ...
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Pin Description (continued) Ball # BGA Name L1 SEC Secondary Reference (Input). This input is a Secondary reference source for synchronization. The module can synchronize to falling edge of the following reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or ...
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Pin Description (continued) Ball # BGA Name K17 JA77P JA 77.76 MHz Clock (LVPECL Output). This differential output provides a low J17 JA77N jitter 77.76 MHz clock. G2 F0o Frame Pulse ST-BUS 2.048 Mbps (Output). This kHz, ...
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Pin Description (continued) Ball # BGA Name D1 FCS Filter Selector (Input). Logic 0 on this pin sets the filter corner frequency to 1.5 Hz, this selection meets requirements of G.813 option 1 and GR-1244 Stratum 3 clocks. Logic 1 ...
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Pin Description (continued) Ball # BGA Name C3 - C8, DGND Ground G5 P7, R2, R3, T1, T2 B12, T6, GC Ground Connections ...
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Pin Description (continued) Ball # BGA Name A4 D4 Data tolerant three-state I/O). Data input/output for the microprocessor port ( Data tolerant three-state I/O). Data input/output for the microprocessor port ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Functional Description The ZL30461 offers a complete timing solution in a BGA module package. The ZL30461 has been designed to provide timing for SDH and SONET equipment, conforming to ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates ...
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In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide preprocessed phase data to the Core PLL including detection of reference clock quality. This preprocessing reduces the load on the Core PLL ...
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For 0.1 Hz filtering applications (FCS=1, FCS2=0) • Wait until the ZL30461 LOCK indicator is high, indicating that it is locked • Pull FCS low • Pull RefAlign low • Hold RefAlign low for 250 µs • Pull RefAlign high ...
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After initiating a reference realignment the ZL30461 will enter Holdover Mode for 200 ns while aligning the internal clocks to remove the static phase error. The ZL30461 will then begin the normal locking procedure. The LOCK pin will remain high ...
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ZL30461 Output Driver LVPECL Driver Note : Vcc = +3.3V Figure 3 - LVPECL Output Termination Circuit 1.4.3 Clock Formats The ZL30461 outputs the following clock and frame pulses: • C1.5o: 1.544 MHz clock with nominal 50% duty cycle • ...
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Figure 4 - C155o and C34/C44 Clock Generation Options 1.4.4 Output Clocks Phase Adjustment The ZL30461 provides three control registers dedicated to programming the output clock phase offset. Clocks C16o, C8o, C4o, C2o and frame pulses F16o, F8o and ...
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Reset == 1 FreeRun Reset 10 MS2, MS1 == 10 forces unconditional return from any state to FreeRun Notes equal != : not equal &= : AND operation 0 --> transition from ...
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Acquisition PLLs that continuously monitor the quality of the incoming reference clocks. This dual architecture enables quick replacement of a poor or failed reference and minimizes the time spent in other states. During this state the ZL30461 can tolerate a ...
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TCXO and Master Clock Frequency Calibration Circuit In an ordinary timing generation module, the Free-run Mode accuracy of generated clocks is determined by the accuracy of the Master Crystal Oscillator. If the Master Crystal Oscillator has a manufacturing tolerance ...
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Hardware and Software Control The ZL30461 offers Hardware and Software Control options that simplify design of basic or complex clock synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing cards without extensive programming. ...
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Control Pins The ZL30461 has six dedicated control pins for selecting modes of operation and activating different functions. These pins are listed below: MS2 and MS1 pins: Mode Select. The MS2 and MS1 inputs select the PLL mode of ...
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Status Pins The ZL30461 has four dedicated status pins for indicating modes of operation and quality of the Primary and Secondary reference clocks. These pins are listed below: LOCK - This output goes to logic 1 when the core ...
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Address Register hex 04 Control Register 2 06 Phase Offset Register 2 07 Phase Offset Register 1 0F Device ID Register 11 Control Register 3 13 Clock Disable Register 1 14 Clock Disable Register 2 19 Core PLL Control Register ...
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Bit Name Mode Select. - MS2 = 0 MS1 = 0 4-3 MS2, MS1 - MS2 = 0 MS1 = 1 - MS2 = 1 MS1 = 0 - MS2 = 1 MS1 = 1 Filter Characteristic Select. (see Table ...
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Bit Name 1 RSV Reserved. 0 RSV Reserved. Table 7 - Status Register 1 (R) (continued) Address Bit Name E3, DS3 or OC-3 Clock Select. Setting this to 0 enables the C155P/N outputs and enables the C34/C44 output ...
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Address Bit Name C16POA7 C16 Phase Offset Adjustment. The eight least significant bits of the phase 7-0 to offset adjustment word. See the Phase Offset Register 2 for details. C16POA0 Address Bit Name Device Identification Number. ...
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Address Bit Name 7-6 RSV Reserved. C16o (16.384 MHz) Clock Disable. When set to 1, this bit tristates the 5 C16odis 16.384 MHz clock output. C8o (8.192 MHz) Clock Disable. When set to 1, this bit tristates the ...
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Address Bit Name 7-3 RSV Reserved. Manual Holdover Release. A change form the MHR bit will release the Core PLL from Auto Holdover when automatic return from holdover is 2 MHR disabled (AHRD is ...
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Address Bit Name 7-5 RSV Reserved. Input Frequency. These two bits identify the Primary Reference Clock frequency 19.44 MHz 4-3 InpFreq1 kHz - 10 = 1.544 MHz - 11 = 2.048 ...
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Address Bit Name Master Clock Frequency Calibration. This most significant byte contains the 31st to 24th bit of the Master Clock Frequency Calibration Register. 7-0 MCFC32-24 See Applications Section 3.3 for a detailed description of how to calculate ...
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System Start-Up Sequence: FREE-RUN --> HOLDOVER --> NORMAL The Free-run to Holdover to Normal transition represents a sequence of steps that will most likely occur during a new system installation or scheduled maintenance of timing cards. The process starts ...
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After detecting any of these anomalies on a reference clock the Acquisition PLL will switch itself into Holdover state forcing the Core PLL to automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0 and ...
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Reset == 1 FreeRun Reset 10 MS2, MS1 == 10 forces unconditional return from any state to FreeRun Figure 9 - Entry into Auto Holdover State and Recovery into Normal Mode by Switching The new reference clock will most ...
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Reset == 1 FreeRun Reset 10 MS2, MS1 == 10 forces unconditional return from any state to FreeRun Two types of transitions are possible: • Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock without ...
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ZL30461 SE C Timing Card (Active Master ZL30461 SE C Timing Card (Active Slave) Figure 11 - Block Diagram of the Master/Slave Timing Protection Switching A detailed description of this ...
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Characteristics 4.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply Voltages 2 Input Voltage * Voltages are with respect to ground (GND) unless otherwise stated. * Exceeding these values may cause permanent damage. Functional operation under ...
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DC Electrical Characteristics* (continued) Characteristics 12 LVDS: Output rise and fall times LVPECL: Differential output 13 voltage LVPECL: High-level output 14 voltage LVPECL: Low-level output 15 voltage LVPECL: Output rise and fall 16 times * Voltages are with respect to ...
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AC Electrical Characteristics* (continued) Parameter 10 Free-Run Accuracy 11 Holdover Frequency Stability 12 Holdover Entry Phase Transient 13 Wander Generation 14 Wander Transfer 15 Jitter Generation Phase Transient Generation 16 (Holdover to Normal transition) Phase Transient Generation 17 (Alternate Reference) ...
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AC Electrical Characteristics - Timing Parameter Measurements - CMOS Voltage Levels* Characteristics 1 Threshold voltage 2 Rise and fall threshold voltage High 3 Rise and fall threshold voltage Low All Signals T IF Figure 12 - Timing Parameters ...
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AC Electrical Characteristics - Microprocessor Timing* Characteristics 1 DS low 2 DS high 3 CS setup 4 DS hold 5 R/W setup 6 R/W hold 7 Address setup 8 Address hold 9 Data read delay 10 Data read hold 11 ...
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AC Electrical Characteristics - ST-BUS and GCI Output Timing* Characteristics 1 F16o pulse width low 2 F8o to F16o delay 3 C16o pulse width low 4 F8o to C16o delay 5 F8o pulse width high 6 C8o pulse width low ...
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AC Electrical Characteristics - DS1, DS2 and C19o Clock Timing* Characteristics 1 C6o pulse width low 2 F8o to C6o delay 3 C1.5o pulse width low 4 F8o to C1.5o delay 5 C19o pulse width high 6 F8o to C19o ...
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C155L C155p tc = 6.47ns C19o tc = 51.44ns Note : Delay is measured from the rising edge of C155P clock (single ended) at 1.25V voltage level to the rising and falling edges of C19o Electrical ...
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Figure 17 - Input Reference to Output Clock Phase Alignment AC Electrical Characteristics - Input Control Timing* Characteristics 1 Input control setup time 2 Input control hold time F8o MS1, MS2 RSEL Figure 18 - Input Control Signal Setup and ...
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AC Electrical Characteristics - E3 and DS3 Output Timing* Characteristics 1 C44o clock pulse width high 2 C11o clock pulse width high 3 C34o clock pulse width high 4 C8.5o clock pulse width high t C44H C44o tc = 22.35ns ...
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Performance Characteristics - Mode Switching* (continued) Characteristics 7 1.5 Hz Filter 8 0.1 Hz Filter Output Phase Continuity (MTIE) 9 Reference switching: PRI => SEC, SEC => PRI 10 Switching from Normal Mode to Holdover Mode 11 Switching from Holdover ...
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Performance Characteristics: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance* Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Interface Measurement Filter 1 OC-3 65 kHz to 1.3 MHz 155.52 Mbps 2 12 kHz to1.3 MHz (Category II) 3 500 ...
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Performance Characteristics: Measured Output Jitter - T1.403 Conformance* ANSI T1.403 Jitter Generation Requirements Jitter Interface Measurement Filter 1 DS1 8 kHz to 40 kHz 1.544 Mbps kHz * Supply voltage and operating temperature are as ...
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Performance Characteristics: Measured Output Jitter - G.732, G.735 to G.739 Conformance* ITU-T G.732, G.735, G.736, G.737, G.738, G739 Jitter Generation Requirements Jitter Interface Measurement Filter 100 kHz 2048 kbits/s * Supply voltage and operating temperature ...
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Performance Characteristics: Measured Output Jitter - G.813 conformance - Option 1 ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-1 65 kHz to 155.52 Mbps 1.3 MHz 2 500 Hz to 1.3 MHz 3 STM-4 250 kHz to ...
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Performance Characteristics: Measured Output Jitter - G.813 Conformance - Option 2 ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-1 12 kHz to 155.52 Mbps 1.3 MHz 2 STM-4 12 kHz to 622.08 Mbps 5 MHz 3 STM-4 ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE ACN DATE APPRD. DIMENSION Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...