ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 12

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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1.3
The DCO is an arithmetic unit that continuously generates a stream of numbers representing the phase-locked
clock. These numbers are passed to the Clock Synthesizer (see Section 1.4) where they are converted into
electrical clock signals of different frequencies.
1.3.1
In Normal Mode, the clock generated by the DCO is phase-locked to the input reference signal and band-limited to
meet network synchronization standards. The ZL30461 provides four software programmable (FCS bit in Control
Reg 1 and FCS2 bit in Control Reg 3) and two hardware selectable (FCS pin) filtering options. The filtering
characteristics are similar to a first order low pass filter with corner frequencies that support international standards:
1.3.2
The ZL30461 is considered locked (LOCK = 1) when the residual phase movement after declaring locked condition
does not exceed 20 ns; as required by standard wander generation MTIE and TDEV tests. To ensure the integrity of
the LOCK status indication, the ZL30461 holds LOCK bit/pin low for a minimum of 65 sec in the 0.1 Hz filtering
mode and 10 sec in the 1.5 Hz filtering mode.
1.3.3
When the ZL30461 finishes locking to a reference an arbitrary phase difference will remain between its output
clocks and its reference; this phase difference is part of the normal operation of the ZL30461. If so desired, the
output clocks can be brought into phase alignment with the PLL reference (see Figure 17) by using the RefAlign
control bit/pin.
Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference
If the ZL30461 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought
into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the
procedures below:
FCS2
In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide
preprocessed phase data to the Core PLL including detection of reference clock quality. This preprocessing
reduces the load on the Core PLL and improves quality of the generated clock.
In Holdover Mode, the Core PLL generates a clock based on data collected from past reference signals. The
Core PLL enters Holdover Mode if the attached Acquisition PLL switches into the holdover state under
external software or hardware control.
(bit)
0
0
1
1
Digitally Controlled Oscillator (DCO)
Filters
Lock Indicator (LOCK)
Reference Alignment (RefAlign)
(pin/bit)
FCS
0
1
0
1
1.5 Hz
0.1 Hz
12 Hz
Filter
6 Hz
Meets requirements of G.813 Option 1 and GR-1244 Stratum 3, Stratum 4E and
Stratum 4 clocks.The maximum phase slope is limited to 41 ns in 1.326 ms.
Meets requirements of G.813 Option 2 and GR-253 for SONET stratum 3. The
maximum phase slope is limited to 885 ns in one second.
This filter configuration limits output phase slope to 1200 µs/sec.
Meets requirements of G.813 Option 1 for SDH Equipment Clocks (SEC) and
GR-1244 for Stratum 4 and Stratum 4E clocks. The maximum phase slope is
limited to 50 ns in 1.326 ms.
Table 1 - Loop Filter Selection
Zarlink Semiconductor Inc.
ZL30461
12
Conformance
Data Sheet