ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 31

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.1.1
The Free-run to Holdover to Normal transition represents a sequence of steps that will most likely occur during a
new system installation or scheduled maintenance of timing cards. The process starts from the RESET state and
then transitions to Free-run state when the device is being initialized. At the end of this process, the ZL30461
should be switched into Normal Mode (with MS2, MS1 set to 00) instead of Holdover Mode. If the reference clock is
available, the ZL30461 will transition briefly into Holdover state to acquire synchronization and switch automatically
to Normal state. If the reference clock is not available, the ZL30461 will stay in Holdover state indefinitely. Whilst in
Holdover state, the Core PLL will continue generating clocks with the same accuracy as in the Free-run Mode,
waiting for a valid reference clock. When the system is connected to the network (or timing card switched to a valid
reference), the Acquisition PLL will quickly synchronize and clear its own Holdover status (PAH bit). This will enable
the Core PLL to start the synchronization process. After acquiring lock, the ZL30461 will automatically switch from
Holdover state to Normal state without system intervention. This transition to the Normal state will be flagged by the
LOCK status bit and pin.
3.1.2
The Normal to Auto-Holdover to Normal transition will usually happen when the Network Element loses its single
reference clock unexpectedly or when it has two references but switching to the secondary reference is not a
desirable option.
The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure 8
“Automatic entry into Auto Holdover State and recovery into Normal mode” at a time when ZL30461 operates in
Normal Mode. This failure is detected by the active Acquisition PLL based on the following FAIL criteria:
•
•
Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm
(±3%).
Phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.
System Start-Up Sequence: FREE-RUN --> HOLDOVER --> NORMAL
Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL
Reset
_____
Reset == 1
unconditional return from
MS2, MS1 == 10 forces
any state to FreeRun
Figure 7 - Transition from Free-Run to Normal Mode
FreeRun
10
MS2, MS1 != 10
MS2, MS1 == 01 or
RefSel change
Zarlink Semiconductor Inc.
Holdover
ZL30461
01
MS2, MS1 == 00
Ref: OK &
31
{Auto}
RefSel change
(Locked)
Normal
00
Ref: OK --> Fail &
MS2, MS1 == 00
{Auto}
Holdover
Auto
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=1 &
MHR 0 --> 1
{Manual}
Ref: Fail --> OK &
MS2, MS1 == 00
& AHRD=0 &
{Auto}
Data Sheet