ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 26

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 07 H
Address: 0F H
Address: 11 H
7-0
7-4
3-0
5-3
2-1
Bit
Bit
Bit
7
6
0
C1.5POA2
C1.5POA0
C16POA7
C16POA0
Name
FCS2
RSV
RSV
RSV
Name
ID7 - 4
ID3 - 0
Name
to
to
Reserved.
Reserved.
C1.5 Phase Offset Adjustment. These three bits allow for changing of the
phase offset of the C1.5o clock relative to the active input reference. The phase
offset is an unsigned number in a range from 0 to 7. Each increment by one
represents phase-offset advancement by 80.96 ns. Example: Writing 010
advances the C1.5o clock by 162 ns, writing 001 delays this clock by 80.96 ns
from this (010) position, writing 000 will remove programmed the offset.
Reserved.
Filter Characteristic Select. (see Table 6 for complimentary FCS bit
description)
- FCS2 = 0, FCS = 0: Filter corner frequency set to 1.5 Hz.
- FCS2 = 0, FCS = 1: Filter corner frequency set to 0.1 Hz.
- FCS2 = 1, FCS = 0: Filter corner frequency set to 12 Hz.
- FCS2 = 1, FCS = 1: Filter corner frequency set to 6 Hz.
Conformance of these filter settings to standards is presented in Table 1.
C16 Phase Offset Adjustment. The eight least significant bits of the phase
offset adjustment word. See the Phase Offset Register 2 for details.
Device Identification Number. These four bits represent the device part number. The
ID number for ZL30461 is 0111.
Device Revision Number. These bits represent the revision number, starts from 0000.
Table 10 - Phase Offset Register 1 (R/W)
Table 12 - Control Register 3 (R/W)
Table 11 - Device ID Register (R)
Zarlink Semiconductor Inc.
Functional Description
ZL30461
Functional Description
26
Functional Description
Data Sheet
Default
Default
0000
0000
000
000
000
0
0