ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 2

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Description
The ZL30461 is a Compact Timing Module, which functions as a complete system clock solution for general
Stratum 3 and SONET/SDH timing applications.
The ZL30461 uses Zarlink's Digital and Analog Phase Locked Loop (DPLL and APLL) technology and can lock to 1
of 4 input frequencies automatically. The module has multiple output clocks ranging from 8 kHz to 155.52 MHz, its
primary output at 77.76 MHz has low jitter performance at less than 40 ps (Pk to Pk). The availability of multiple
clocks and features such as holdover and out-of-range detection enable the ZL30461 to be used on the master
timing card as well as the linecard.
Note: All undefined pins must be left unconnected.
Pin Description
Ball # BGA
M1
Name
PRI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Primary Reference (Input). This input is a Primary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 0 is applied to the RefSel input pin.
This pin is internally pulled to V
1
2
3
Figure 2 - 240 Pin BGA Top View
4
5
Zarlink Semiconductor Inc.
6
ZL30461
7
8
2
9
10
DD1
11
.
Description
12
13
14
15
16
17
Data Sheet