ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 22

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.1.2
The ZL30461 has four dedicated status pins for indicating modes of operation and quality of the Primary and
Secondary reference clocks. These pins are listed below:
LOCK - This output goes to logic 1 when the core PLL is locked to the selected Acquisition PLL.
HOLDOVER - This output goes to logic 1 when the Core PLL enters Holdover Mode. The Core PLL will switch to
Holdover Mode if the respective Acquisition PLL enters Holdover Mode or if the mode select pins or bits are set to
Holdover (MS2, MS1 = 01).
PRIOR - Primary Reference Acceptance Range. This output goes to logic 1 when the primary reference
frequency is outside of the acquisition PLL ±12 ppm acceptance range.
SECOR - Secondary Reference Acceptance Range. This output goes to logic 1 when the secondary reference
frequency is outside of the acquisition PLL ±12 ppm acceptance range.
2.2
Software control is enabled by setting the HW pin to logic 0 (HW = 0). In this mode all hardware control pins (inputs)
are disabled, but the status (outputs) are still enabled. The ZL30461 has 18 registers that provide all the
functionality available in Hardware control and also offer advanced control and monitoring that is only available in
Software control (see Figure 6 “Hardware and Software Control options”).
2.2.1
The ZL30461 has seven control bits as is shown in Figure 6 “Hardware and Software Control options”. Five bits
replace the five hardware control pins: MS2, MS1, FCS, RefSel and RefAlign (Table5: Control Register 1), and two
bits support recovery from Auto Holdover Mode: AHRD and MHR (Table 15: Core PLL Control Register).
In addition to the Control bits shown in Figure 6 “Hardware and Software Control Options”, the ZL30461 has a
number of bits and registers that are accessed infrequently or during configuration only e.g. Phase Offset
Adjustment or Master Clock Frequency Calibration.
2.2.2
The ZL30461 has nine status bits (see Figure 6 “Hardware and Software Control options”, Tables 6, 17 and 18).
Four bits perform the same function as their equivalent status pins (PRIOR, SECOR, LOCK and HOLDOVER). Five
bits perform two functions. Bits FLIM, PAFL, SAFL indicate drift of the reference clock frequencies beyond the
capture range of Acquisition and Core PLLs and bits PAH and SAH show entry of Primary and Secondary
Acquisition PLLs into Holdover Mode. These bits are described in detail in Section 2.2.3. The status pins are
enabled when the ZL30461 operates in software control and they can be used to trigger interrupts.
2.2.3
Addresses: 00H to 6FH
Address
hex
00
01
Software Control
Status Pins
Control Bits
Status Bits
ZL30461 Register Map
Control Register 1
Status Register 1
Register
Table 5 - ZL30461 Register Map
Write
Read
Zarlink Semiconductor Inc.
R/W
R
ZL30461
RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign
PRIOR, SECOR, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv
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Function
Data Sheet