ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 7

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
Note 1:
Ball # BGA
M17,N17,
E16,E17,
F15,G17,
H17,L17,
P17,R17,
T17,
A4
B4
A3
B3
U4
U3
U1
U2
T3
Connections relate to the Analog PLL stage, if the jitter attenuated outputs are not being used, you do not need to make these
connections.
Name
Tms
Tdo
Tclk
Trst
NC
Tdi
D4
D5
D6
D7
Data 4 (5 V tolerant three-state I/O). Data input/output for the microprocessor port
(D0 - D7).
Data 5 (5 V tolerant three-state I/O). Data input/output for the microprocessor port
(D0 - D7).
Data 6 (5 V tolerant three-state I/O). Data input/output for the microprocessor port
(D0 - D7).
Data 7 (5 V tolerant three-state I/O). Data input/output for the microprocessor port
(D0 - D7), D7 is the most significant bit.
IEEE1149.1a Test Data Output. JTAG serial data is output on this pin on the falling
edge of Tclk clock. If not used, this pin should be left unconnected.
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled to V
used, this pin should be left unconnected.
IEEE1149.1a Test Clock Signal (3.3 V input). Input clock for the JTAG test logic.
If not used, this pin should be pulled up to V
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG TAP
controller. This pin should be pulsed low on power-up to ensure that the TAP is
reset. This pin is internally pulled down to DGND. If not used, this pin should be left
unconnected.
Do NOT connect to these pins, internal connections
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test instructions
and data. This pin is internally pulled up to V
unconnected.
Zarlink Semiconductor Inc.
ZL30461
7
Description
DD
DD1
.
. If not used, this pin should be left
DD
Data Sheet
. If not