ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet
ZL50010/GDC
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ZL50010/GDC Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512 Channel DX with Enhanced ZL50010/QCC 160 Pin LQFP ZL50010/GDC 144 Ball LBGA • Per-stream output channel and output bit delay programming with fractional bit advancement • ...
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Applications • Small and medium digital switching platforms • Access Servers • Time Division Multiplexers • Computer Telephony Integration • Digital Loop Carriers Description The device has 16 ST-BUS inputs (STi0-15) and 16 ST-BUS outputs (STo0-15 non-blocking ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MTIE ...
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Figure 1 - ZL50010 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 46 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - FPi and CKi Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NC 122 NC 123 A2 124 A3 125 A4 126 VSS 127 VDD 128 A5 129 A6 130 A7 131 A8 132 A9 133 A10 134 A11 135 VSS 136 VDD 137 STi0 138 STi1 139 STi2 140 STi3 ...
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PINOUT DIAGRAM: (as viewed through top of package) A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner ODE FPo2 FPo0 SEC_ B CKo2 CKo1 FPo1 CKo0 C STo2 STo1 STOHZ PRI_ 0 ...
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Pin Description LQFP Pin LBGA Ball Number Number 10, 23, 33, D5, D6, D7 43, 48, 58, E9 68, 78, 92, F4, F9 102, 113, G4 127, 136, H4 146, 156 J6, J7 18, 21, D4, D9 E5, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number C10 14 A6, A5, B6, B5 ZL50010 ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number D2, C2, C1 E2, E1, F1 ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number C3, D3, E4, E3 STOHZ F3, G3, G1, G2 STOHZ J3, K1, L1, J2 STOHZ 8 ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number 157 D11 158 C11 1, 2, 29 82, 119 - 122, 159, 160 ZL50010 Name RESET Device Reset (5 V Tolerant Input): This input ...
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Device Overview The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and timing for the ST-BUS input streams with various data rates (2.048 Mbps, 4.096 Mbps and/or 8.192 Mbps). ...
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Users have to program the CKIN2 - 0 bits in the Control Register (CR), for the width of the frame pulse low cycle and the frequency of the input clock. See Table 1 for the programming of the CKIN0, CKIN1 ...
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ST-BUS Input Timing When the negative input frame pulse and negative input clock formats are used, the input frame boundary is defined by the falling edge of the CKi input clock while the FPi is low. When the input ...
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ST-BUS Output Data Rate and Output Timing The device has 16 ST-BUS serial data outputs. Any of the 16 outputs can be programmed to deliver different data rates at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps. 2.2.1 ST-BUS Output ...
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The device also delivers positive or negative output frame pulse and ST-BUS output clock formats via the programming of the FP0P, FP1P, FP2P, CK0P, CK1P and CK2P bits in the Internal Mode Selection (IMS) register. By default, the device delivers ...
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FPo2 FP2P = 0 FPo2 FP2P = 1 CKo2 (32.768 MHz) CK2P = 0 CKo2 (32.768 MHz) CK2P = 1 Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 0 FPo2 FP2P = 0 FPo2 FP2P ...
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ST-BUS Output Timing By default, the output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clock while the FPo0, FPo1 or FPo2 output frame pulse goes low respectively. When the output data ...
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Serial Data Input Delay and Serial Data Output Offset Various registers are provided to adjust the input and output delays for every input and every output data stream. The input and output channel delay can vary from 0 to ...
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Fractional Input Bit Delay Programming In addition to the input bit delay feature, the device allows users to change the sampling point of the input bit. By default, the sampling point is at 3/4 bit. Users can change the ...
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Output Bit Delay Programming This feature is used to delay the output data bit of individual output streams with respect to the output frame boundary. Each output stream can have its own bit delay value. By default, all output ...
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External High Impedance Control, STOHZ The STOHZ outputs are provided to control the external tristate ST-BUS drivers for per-channel high impedance operations. The STOHZ outputs are sent out in 32 128 ...
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Data Delay Through The Switching Paths To maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output channel delay modes affect the data delay through various switching paths due to additional ...
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By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (T) is frames + (m-n). Figure 21 shows the throughput delay when the input Ch0 is switched to ...
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When the input channel delay and the output channel delay are enabled, the data throughput delay is frames - α + β + (m-n). Figure 24 shows the data throughput delay when the input Ch0 is switched ...
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Memory block programming procedure: (Assumption: The MBPE and MBPS bits are both low at the start of the procedure) • Program Bit (BPD0 to BPD2) in the IMS (Internal Mode Selection) register. • Set the Memory Block ...
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BER Count Register (BCR) - Contains the number of counted errors. When the error count reaches Hex FFFF, the bit error counter will stop so that it will not overflow. Consequently the BER Count Register will also stop at ...
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STIN#QEN3 1 Replace LSB of every channel in Quadrant 3 with "1" bit replacement occurs in Quadrant 3 Table 13 - Quadrant Frame 3 LSB Replacement 2.8 Microprocessor Port The device supports the non-multiplexed microprocessor. The microprocessor port ...
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Bit Table 14 - DPLL Operating Mode Settings The DPLL intrinsic jitter is 6.25 ns peak to peak. In Master and Freerun modes, the DPLL intrinsic jitter will be added onto the ST-BUS outputs. ...
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Master Mode Reference Switching The DPLL monitors both the primary and secondary reference. When the reference the DPLL is currently synchronized to becomes invalid, the DPLL’s response depends on which one of the failure detect modes has been chosen: ...
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DPLL Freerun Mode DPLL Freerun mode is selected by the setting in Table 14. In Freerun mode, the DPLL is not synchronized to any of the reference inputs. The DPLL synthesizes the internal clock MCKTDM very accurately. MCKTDM provides ...
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DPLL Functional Description Figure 25 shows the functional block diagram of the DPLL. Major functional blocks are described in the following sections. When the DPLL is in Master or Freerun mode, the APLL input is C20i from the oscillator ...
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Reference Select and Frequency Mode Mux Circuits The DPLL accepts two simultaneous reference inputs and operates on their rising edges. The State Machine output REF_SELECT chooses either the primary reference (PRI_REF_INT signal) or the secondary reference (SEC_REF signal) as ...
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LOS Control Circuit LOS Control uses the results from the reference monitors to influence the transition of the State Machine. The outputs of LOS Control are affected by the choice of the failure detect mode (one of autodetect, forced ...
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Maximum Time Interval Error (MTIE) Circuit The MTIE circuit prevents any significant change in the DPLL output clock phase during a reference switch. The input references can have any relationship between their phases. The DPLL output follows the selected ...
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Phase Detector - The Phase Detector compares the virtual reference signal from the MTIE circuit (REF_VIR) with the FEEDBACK signal from the Frequency Select Mux. It provides an error signal corresponding to the phase difference between the signals’ rising edges. ...
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DPLL Performance The following are some synchronizer performance indicators and their definitions. The performance of the DPLL is also indicated. 2.11.1 Intrinsic Jitter Intrinsic jitter is the jitter produced by a synchronizer and is measured at its output. It ...
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Figure 29 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies Figure 30 - Detailed DPLL Jitter Transfer Function Diagram (Wander Transfer Diagram) ZL50010 41 Zarlink Semiconductor Inc. Data Sheet ...
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Holdover Accuracy Holdover accuracy is defined as the absolute tolerance of an output clock signal, when the synchronizer is not locked to an external reference signal but is operating using storage techniques. In the Holdover state, the DPLL is ...
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Phase Lock Time The Phase Lock Time is the time it takes a synchronizer to phase lock to the input signal. Phase lock occurs when the input and the output signals are not changing in phase with respect to ...
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Oscillator Requirements In DPLL Master and Freerun modes, the APLL module requires a 20 MHz clock source at the XTALi pin. The 20 MHz clock can be generated by connecting an external crystal oscillator to the XTALi and XTALo ...
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External Clock Oscillator When an external clock oscillator is used, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels and duty cycle. ± For applications requiring 32 ppm ...
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Device Reset and Initialization The RESET pin is used to reset the device. When the pin is low, it synchronously puts the device into its reset state. It disables the STo0 - 15 outputs, drives the STOHZ 0 - ...
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Instruction Register The ZL50010 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four- bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is ...
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Register Address Mapping External Address A11 - A0 000 H 001 H 010 H 011 H 012 H 030 H 031 H 032 H 100 H 101 H 102 H 103 H 104 H 105 H 106 H 107 ...
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ZL50010 External CPU Address Access A11 - A0 11D R/W Stream14 Input Delay Register, SIDR14 H 11E R/W Stream15 Input Control Register, SICR15 H 11F R/W Stream15 Input Delay Register, SIDR15 H 200 R/W Stream0 Output Control Register, SOCR0 H ...
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Detail Register description External Read/Write Address: 000 H Reset Value: 0000 SLV FBD CKIN CKIN Bit Name 15 Unused Reserved. In normal functional mode, these bits MUST be set ...
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External Read/Write Address: 000 H Reset Value: 0000 SLV FBD CKIN CKIN CKIN Bit Name 3 OSB Output Stand By Bit: This bit enables the STo0 - 15 and ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP FPINP Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 CKINP ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP FPINP Bit Name 0 MBPS Memory Block Programming Start: A zero to one transition of this bit starts the memory block ...
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External Read/Write Address: 011 H Reset Value: 0000H Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero BL7 ...
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External Read/Write Address: 030 H Reset Value: 0000 MRST FDM1 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 ...
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External Read/Write Address: 030 H Reset Value: 0000 MRST FDM1 Bit Name FP1 - FP0 PRI_REF Frequency Selection Bits: These bits are used to specify the ...
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External Read/Write Address: 031 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 9 ...
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External Read/Write Address: 100 , 102 , 104 H H Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 0 ...
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External Read/Write Address: 100 , 102 , H H Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 0 0 ...
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External Read/Write Address: 110 , 112 , 114 H H Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 0 0 ...
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External Read/Write Address: 110 , 112 , H H Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 SICR12 0 0 ...
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External Read/Write Address: 101 , 103 , H H Reset Value: 0000 SIDR0 SIDR1 SIDR2 SIDR3 SIDR4 0 0 ...
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External Read/Write Address: 111 , 113 , H H Reset Value: 0000 SIDR8 SIDR9 SIDR10 SIDR11 ...
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External Read/Write Address: 200 , 202 , H H Reset Value: 0000 SOCR0 SOCR1 SOCR2 SOCR3 SOCR4 0 0 ...
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External Read/Write Address: 210 , 212 , H H Reset Value: 0000 SOCR8 SOCR9 SOCR10 SOCR11 ...
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External Read/Write Address: 201 , 203 , H H Reset Value: 0000 SOOR0 SOOR1 SOOR2 SOOR3 SOOR4 0 0 ...
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External Read/Write Address: 211 , 213 , H H Reset Value: 0000 SOOR8 STO8C D6 SOOR9 STO9C D6 SOOR10 STO10 CD6 SOOR11 ...
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Memory Address Mappings When A11 is high, the data or the connection memory can be accessed by the microprocessor port. The Bit 0 to Bit 2 in the control register determine the access to the data or connection memory ...
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Connection Memory Bit Assignment When the CMM bit (Bit0) is zero, the connection is in normal switching mode. When the CMM bit is one, the connection memory is in special transmission mode SSA3 SSA2 SSA1 Bit ...
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Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Input Voltage 3 Input Voltage (5 V tolerant inputs) 4 Continuous Current at digital outputs 5 Package power dissipation 6 Storage temperature * Exceeding these values may cause permanent damage. Functional ...
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AC Electrical Characteristics Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. AC Electrical Characteristics Characteristic 1 FPi Input Frame Pulse Width 2 FPi Input ...
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FPi t CKi Input Frame Boundary Figure 33 - Frame Pulse Input and Clock Input Timing Diagram AC Electrical Characteristics Variation Characteristic 1 CKi Input Clock cycle-to-cycle variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical ...
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AC Electrical Characteristics cycle Variation Characteristic 1 FPi Input Frame Pulse cycle-to-cycle variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25° 3.3 V and are for design aid only: not ...
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AC Electrical Characteristics - Reference Input Timing Characteristic 1 PRI_REF, SEC_REF Period 2 PRI_REF, SEC_REF High Time 3 PRI_REF, SEC_REF Low Time 4 PRI_REF, SEC_REF Rise/Fall Time 5 PRI_REF, SEC_REF Period 6 PRI_REF, SEC_REF High Time 7 PRI_REF, SEC_REF Low ...
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AC Electrical Characteristics - Input and Output Frame Boundary Alignment Characteristic 1 Input and Output Frame Offset in DPLL Master Mode 2 Input and Output Frame Offset in DPLL Bypass Mode FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi ...
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AC Electrical Characteristics Characteristic 1 FPo0 Output Pulse Width 2 FPo0 Output Delay from the CKo0 falling edge to the output frame boundary 3 FPo0 Output Delay from the output frame boundary to the CKo0 Rising edge 4 CKo0 Output ...
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AC Electrical Characteristics Characteristic 1 FPo1 Output Pulse Width 2 FPo1 Output Delay from the CKo1 falling edge to the output frame boundary 3 FPo1 Output Delay from the output frame boundary to the CKo1 Rising edge 4 CKo1 Output ...
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AC Electrical Characteristics Characteristic 1 FPo2 Output Pulse Width 2 FPo2 Output Delay from the CKo2 falling edge to the output frame boundary 3 FPo2 Output Delay from the output frame boundary to the CKo2 Rising edge 4 CKo2 Output ...
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AC Electrical Characteristics Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are at ...
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AC Electrical Characteristics Characteristic 1 STo Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are 3.3 V and ...
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AC Electrical Characteristics Characteristic 1 STo Delay - Active to High-Z STo Delay - High-Z to Active 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 Output Driver Enable (ODE) Delay - High-Z to Active 2.048 Mbps 4.096 Mbps 8.192 Mbps 2 ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 DS delay from the rising edge of DTA to the falling edge ...
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AC Electrical Characteristics Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 TDi Input Hold Time 8 TDo ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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