ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 50

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7.0
12 - 10
External Read/Write Address: 000
Reset Value: 0000
Bit
15
14
13
9
8
7
6
5
4
15
0
Detail Register description
SLV
14
CKIN2-0
Unused
FBDEN
CKFP2
CKFP1
CKFP0
MBPE
Name
CBER
SBER
SLV
FBD
13
EN
H
CKIN
12
2
Reserved. In normal functional mode, these bits MUST be set to zero.
DPLL Bypass Mode Enable.
When this bit is zero, the DPLL is in Master or Freerun mode. When this bit is high, the
DPLL is in Bypass mode.
Frame Boundary Determination Disable.
When this bit is low, the long term frame boundary determination mode is disabled.
When it is high, the determination mode is enabled.
Set this bit from low to high after waiting for 600 µs upon device power up.
Input ST Bus Clock (CKi) and Frame Pulse (FPi) Selection.
Output ST Bus clock CKo2 and frame pulse FPo2 Selection.
When this bit is low, CKo2 is 32.768 MHz clock and FPo2 is 30 ns wide frame pulse
When this bit is high, CKo2 is 16.384 MHz clock and FPo2 is 61 ns wide frame pulse
Output ST Bus clock CKo1 and frame pulse FPo1 Selection.
When this bit is low, CKo1 is 16.384 MHz clock and FPo1 is 61 ns wide frame pulse
When this bit is high, CKo1 is 8.192 MHz clock and FPo1 is 122 ns wide frame pulse
Output ST Bus clock CKo0 and frame pulse FPo0 Selection.
When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse
When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse
Bit Error Rate Counter Clear: When this bit is high, it resets the internal bit error
counter and the content of the bit error count register (BCR) to zero. Upon completion of
the reset, set this bit to zero.
Bit Error Rate Test Start: When this bit is high, it enables the BER transmitter and
receiver; starts the bit error rate test. The bit error test result is kept in the bit error count
(BCR) register. Upon the completion of the BER test, set this bit to zero.
Memory Block Programming Enable: When this bit is high, the connection memory
block programming mode is enabled to program Bit 0 to Bit 2 of the connection memory.
When it is low, the memory block programming mode is disabled.
CKIN
H
11
1
CKIN
Table 17 - Control Register (CR) Bits
10
0
CKIN2 - 0
011 - 111
CKFP
000
001
010
9
2
Zarlink Semiconductor Inc.
ZL50010
CKFP
8
1
50
CKFP
7
0
FPi Low Cycle
Description
122 ns
244 ns
61 ns
CBER
6
SBER
Reserved
5
MBPE
4
16.384 MHz
8.192 MHz
4.096 MHz
OSB
CKi
3
MS2
2
MS1
Data Sheet
1
MS0
0