ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 42

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.11.5
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when the synchronizer is not
locked to an external reference signal but is operating using storage techniques.
In the Holdover state, the DPLL is not locked to any reference. The DPLL generates its output clock MCKTDM
using values which were stored while the DPLL was locked to the selected reference in the Normal state. The
values were stored 32 ms to 64 ms prior to exiting from the Normal state.
Two factors affect the holdover accuracy: large jitter on the reference prior to the state change, and the oscillator
frequency drift since the state change. Note that it is the change in the oscillator frequency between the Normal and
Holdover states which affect holdover accuracy, not the absolute frequency of the oscillator.
The DPLL master clock is derived from the oscillator. When the DPLL is in lock, the DPLL output frequency is
exactly the same as that of the input reference. The DPLL will compensate for any changes in the absolute
frequency of the oscillator. In Holdover, the DPLL output frequency is generated using values stored while the DPLL
was in lock. Thus the DPLL can no longer compensate for changes in the oscillator frequency. The holdover
frequency will change if the oscillator frequency has deviated since the DPLL was in lock.
When there was no jitter in the reference, and there is no change in the oscillator frequency, the DPLL holdover
accuracy is within +/-0.07 ppm, which translates into maximum 49 frame slips (6.125 ms) in 24 hours.
Any change in the oscillator frequency since the transition out of the Normal state will change the holdover
frequency. For example, a +/-32 ppm oscillator may have a temperature coefficient of +/-0.1 ppm/°C. Thus a 10°C
change since the DPLL was last in the Normal state will change the holdover frequency by an additional +/-1 ppm,
which is much greater than the +/-0.07 ppm of the DPLL.
2.11.6
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is defined by the Loop Filter circuit and is equal to +/- 298 ppm.
Note that the locking range is related to the oscillator frequency. If the oscillator frequency is -100 ppm, the whole
locking range also shifts by -100 ppm downwards to become -398 ppm to +198 ppm.
2.11.7
The phase slope, or phase alignment speed, is the rate at which a given signal changes phase with respect to an
ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally
equal to the value of the final output signal or final input signal. Many telecom standards state that the phase slope
may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). This can be achieved by limiting the phase
detector output to 61 ppm or less.
For the DPLL, the Phase Slope Limiter circuit limits the maximum phase slope to 56 ppm or 7 ns/125 µs. The phase
slope limit meets Telcordia GR-1244-CORE requirements.
2.11.8
MTIE (Maximum Time Interval Error) is the maximum peak to peak delay between a given timing signal and an
ideal timing signal within a particular observation period.
For the DPLL, MTIE is less than 21 ns per reference switch.
Holdover Accuracy
Locking Range
Phase Slope
MTIE
Zarlink Semiconductor Inc.
ZL50010
42
Data Sheet