ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 19

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The device also delivers positive or negative output frame pulse and ST-BUS output clock formats via the
programming of the FP0P, FP1P, FP2P, CK0P, CK1P and CK2P bits in the Internal Mode Selection (IMS) register.
By default, the device delivers the negative output frame pulse and negative output clock formats.
Figure 8 to Figure 13 describe the usage of the CKFP0, CKFP1, CKFP2, FP0P, FP1P, FP2P, CK0P, CK1P and
CK2P in the Control Register and Internal Mode Selection Register:
(16.384 MHz)
(16.384 MHz)
(4.096 MHz)
(4.096 MHz)
(8.192 MHz)
(8.192 MHz)
(8.192 MHz)
(8.192 MHz)
CKOP = 1
CKOP = 0
CKOP = 0
CKOP = 1
CK1P = 1
FPOP = 0
CK1P = 0
CK1P = 0
CK1P = 1
FP0P = 0
FP0P = 1
FP1P = 0
FP1P = 1
FP1P = 0
FPOP =1
FP1P =1
(8 kHz)
CKo1
CKo0
CKo0
CKo0
CKo1
CKo1
CKo0
CKo1
FPo0
FPo0
FPo0
FPo0
FPo1
FPo1
FPo1
FPo1
Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 0
Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 1
Figure 8 - FPo0 and CKo0 Output Timing when the CKFP0 Bit = 0
Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 Bit = 1
Zarlink Semiconductor Inc.
ZL50010
19
Data Sheet