ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 30

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

•
As described above, the SBER bit in the control register controls the BER transmitter and receiver. To carry out the
BER test, users should set the SBER bit to zero to disable the BER transmitter during the programming of the
connection memory for the BER test. When the BER transmitter is disabled, the transmitter output is all ones.
Hence any output channel whose connection memory has been programmed to BER test mode will also output all
ones. Upon the completion of programming the connection memory for the BER test, set the SBER bit to one to
start the BER transmitter and receiver for the BER testing. They must be allowed to run for several frames (2
frames plus the network delay between STo and STi) before the BER receiver can correctly identify errors in the
pattern. Thus after this time the bit error counter should be reset by using the CBER bit in the Control Register - set
CBER to one then back to zero. From now on, the count will be the actual number of errors which occurred during
the test. The count will stop at FFFF and the counter will not increment even if more errors occurred.
2.7
By programming the input stream control registers (SICR0 to 15), users can divide 1 frame of input data into 4
quadrant frames and can force the Least Significant Bit (LSB, bit 0 in Figure 7 on page 17) of every input channel in
these quadrants into "1" for the bit robbed signalling purpose. The 4 quadrant frames are defined as shown in
Table 9.
When a quadrant frame enable bit (STIN#QEN0, STIN#QEN1, STIN#QEN2 or STIN#QEN3) is set to high, the LSB
of every input channels in the quadrant is forced to "1". See Table 10 to Table 13 for details:
BER Count Register (BCR) - Contains the number of counted errors. When the error count reaches Hex
FFFF, the bit error counter will stop so that it will not overflow. Consequently the BER Count Register will
also stop at FFFF. The CBER bit in the Control Register is used to reset the bit error counter and the BER
Count Register.
2.048 Mbps
4.096 Mbps
8.192 Mbps
Data Rate
Quadrant frame programming
STIN#QEN0
STIN#QEN1
STIN#QEN2
1
0
1
0
1
0
Quadrant 0
Ch 0 to 15
Ch 0 to 31
Ch 0 to 7
Table 9 - Definition of the Four Quadrant Frames
Table 10 - Quadrant Frame 0 LSB Replacement
Table 11 - Quadrant Frame 1 LSB Replacement
Table 12 - Quadrant Frame 2 LSB Replacement
Replace LSB of every channel in Quadrant 0 with "1"
No bit replacement occurs in Quadrant 0
Replace LSB of every channel in Quadrant 1 with "1"
No bit replacement occurs in Quadrant 1
Replace LSB of every channel in Quadrant 2 with "1"
No bit replacement occurs in Quadrant 2
Zarlink Semiconductor Inc.
ZL50010
Quadrant 1
Ch 16 to 31
Ch 32 to 63
Ch 8 to 15
30
Action
Action
Action
Quadrant 2
Ch 32 to 47
Ch 64 to 95
Ch 16 to 23
Ch 96 to 127
Quadrant 3
Ch 24 to 31
Ch 48 to 63
Data Sheet