ZL50010/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50010/GDC Datasheet - Page 34

• Manufacturer Part Number: ZL50010/GDC
• Description: Flexible 512 Channel DX with Enhanced DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.9.2
DPLL Freerun mode is selected by the setting in Table 14. In Freerun mode, the DPLL is not synchronized to any of
the reference inputs. The DPLL synthesizes the internal clock MCKTDM very accurately. MCKTDM provides timing
for the TDM switching function and for the ST-BUS outputs. Since the DPLL is not synchronized to any of the
reference inputs, the ST-BUS outputs are also not synchronized to any of the reference inputs.
The DPLL can switch to the Freerun mode at any time. Freerun mode is typically used when a master clock
source is required, or immediately following system power-up before network synchronization is achieved. If a
ZL50010 is to be operated exclusively in Freerun mode, then its ST-BUS output clock and frame pulse must be
used as the ST-BUS input clock and frame pulse to all TDM devices in the system, including the device itself.
2.9.3
DPLL Bypass mode is selected by setting high bit 14 of the Control Register (CR), as shown in Table 14. The DPLL
is completely bypassed and the APLL takes its input from CKi instead of the oscillator. The APLL multiplies the ST-
BUS input clock CKi with an appropriate frequency multiplication factor to generate the internal clock MCKTDM.
MCKTDM is synchronized to CKi. MCKTDM provides timing for the TDM switching function and for the ST-BUS
outputs. Hence the ST-BUS outputs are synchronized to CKi. The DPLL intrinsic jitter will not be added onto the ST-
BUS outputs because the DPLL is completely bypassed.
In this mode, the APLL takes its input from CKi instead of the oscillator. If the device is to be used in this mode only,
the oscillator clock is not required and the external crystal oscillator or clock oscillator can be omitted. If the crystal
oscillator or clock oscillator is omitted, the XTALi pin must be held low and the XTALo pin must be left unconnected.
Bypass mode is used when another device, such as another ZL50010 in Master mode, is providing system timing.
DPLL Freerun Mode
DPLL Bypass Mode
Zarlink Semiconductor Inc.
ZL50010
34
Data Sheet